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Student Number 975203022
Author Jhih-ciang Jiang(姜智強)
Author's Email Address ciangs1984@gmail.com
Statistics This thesis had been viewed 515 times. Download 210 times.
Department Communication Engineering
Year 2011
Semester 1
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Design and FPGA Implementation of a Real-Time OFDM Transceiver for Power Line Communications
Date of Defense 2011-10-07
Page Count 93
Keyword
  • OFDM
  • Power Line Communications
  • Transceiver
  • Abstract Power line communication (PLC) system, which adopts the power line network as the transmission medium, enables broadband internet access across the house through existing AC electrical wiring. In this thesis, we design and implement a real-time OFDM transceiver for power line communications on a platform which consists of off-the-shelf digital-to-analog/analog-to-digital converters (DAC/ADC), power line coupling circuit and an FPGA board. The digital signal processing units required for the real-time OFDM transceiver, which includes OFDM symbol synchronizer, FFT processor, channel estimator/equalizer, hard decision logics, symbol/bit deinterleaver and viterbi decoder, is implemented on the FPGA. The spectral range of the transmitted signal is specified to be from 2.3MHz to 20MHz. With 64-QAM modulation and a convolutional code of code rate 1/2, the throughput of the transceiver system is around 42.5Mbps.
    Table of Content 摘    要 i
    ABSTRACT ii
    誌謝 iii
    目錄 iv
    圖目錄 vii
    表目錄 xi
    第一章 緒論 1
    1-1 研究動機與背景 1
    1-2 章節提要 2
    第二章 電力線通道特性 3
    2-1 電力線通道特性簡介 3
    2-1-1 電力線通道雜訊 3
    2-1-2 電力線通道阻抗 4
    2-1-3 電力線通道衰減 5
    2-1-4 電力線通道多重路徑效應5
    2-2 電力線實際通道量測 6
    第三章 電力線通訊系統簡介 13
    3-1 正交分頻多工系統簡介 13
    3-1-1 OFDM調變原理 13
    3-1-2 CP-OFDM簡介 17
    3-2 電力線通訊系統規格與參數介紹 19
    3-2-1 PLC系統規格與參數 19
    3-2-2 PLC系統架構 23
    第四章 電力線通訊系統硬體架構 28
    4-1 時序同步器(Timing Synchronizer) 28
    4-1-1 延遲相關器(Delay Correlator) 29
    4-1-2 峰值檢測器(Peak Detector) 31
    4-1-3 訊號偵測器(Signal Detector) 32
    4-1-4 符碼同步器(Symbol Synchronizer) 35
    4-2 快速傅立葉轉換處理器(FFT Processor) 36
    4-2-1 蝶型運算器架構 38
    4-2-2 座標軸數位旋轉計算器 40
    4-2-3 旋轉因子產生單元 42
    4-2-4 FFT時序控制 43
    4-2-5 位元反轉排序 44
    4-3 通道估測/等化器(Channel Estimator/Equalizer) 46
    4-3-1 通道估測器 46
    4-3-2 通道等化器 47
    4-4 硬式決策器(Hard Decision) 50
    4-5 訊號解交錯器(Symbol/Bit Deinterleaver) 51
    4-6 腓特比解碼器(Viterbi Decoder) 55
    第五章 硬體設計與實現 57
    5-1 系統設計流程 57
    5-2 定點數模擬(Fixed-Point Simulation) 58
    5-3 電路合成報告 72
    5-4 平台架構 75
    第六章 結論 77
    參考文獻 78
    Reference [1]H. Meng. Y.L. Guan and S. Chen,“Modeling and Analysis of Noise Effects on Broadband Power-Line Communications,”IEEE Trans. on Power Delivery, vol. 20,Issue 2,pp 630-637, April 2005.
    [2]蒲冠志, 電力線通訊(PLC)系統工程系列專刊(五) ─ 電力線通訊訊號傳輸特性與實測
    [3]M. Zimmermann and K. Dostert, “A Multipath Model for the Powerline Channel, ”IEEE Trans. Communications, vol. 50, Issue 4, pp. 553-559, April. 2002.
    [4]HomePlug AV White Paper.Available: http://www.homeplug.org
    [5]Ching-Huei Zheng,“A Baseband Digital Signal Processor for HomePlug AV Applications, ”National Tsing Hua University, 2006.
    [6]ETSI EN 300 744, Digital Video Broadcasting(DVB), Framing structure channel coding and modulation for digital terrestrial television. European Standard.
    [7]Shousheng He and M. Torkelson, “Designing Pipeline FFT Processor for OFDM (de) Modulation, ”URSI Int. Symp. Signals, Systems, and Electronics,vol. 29,pp 257-262, Oct. 1998.
    [8]Ping-Chun Wang, “Design and Implementation of Variable-Length Fast Fourier Transform Processor in OFDM Systems, ” National Central University,July 2007.
    [9]Ray Andraka, “A survey of CORDIC algorithms for FPGA based computers,” 1998 ACM/SIGDA Sixth International Symposium on Field programmable gate arrays, 191-200, 1998.
    [10]Chia-Hung Kuo, “Design and Implementation of Viterbi Decoder for Multi-Rate Convolutional Code in DVB-T System, ” National Central University Thesis, July 2010.
    Advisor
  • Yih-Min Chen(陳逸民)
  • Files
  • 975203022.pdf
  • approve in 2 years
    Date of Submission 2011-10-20

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