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Student Number 975203013
Author Chia-hung Kuo(郭家宏)
Author's Email Address 975203013kuo@gmail.com
Statistics This thesis had been viewed 605 times. Download 614 times.
Department Communication Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Design and Implementation of Viterbi Decoder for Multi-Rate Convolutional Code in DVB-T System
Date of Defense 2010-07-06
Page Count 100
Keyword
  • BICM
  • COFDM
  • Convolution Code
  • DVB-T
  • Maximum Likelihood Decoding
  • Abstract The most efficiently decoder in convolution decode is Viterbi algorithm which is using maximum likelihood criterion, it apply in many COFDM and wireless communication system widely. Viterbi decode implementation is still using hard decision to calculate Hamming distance in 802.11a system; however its ability that error protection on transmitted data is limited. In this thesis, we discuss the design/implementation issues of Viterbi decoder for multi-rate convolutional code in DVB-T system. The issues include: soft-decision of QAM symbol, quantization levels of soft-decision, channel-state-information, traceback depth and iterative decoding for BICM in DVB-T system.
    Table of Content 摘要I
    ABSTRACTII
    誌謝II
    目錄III
    圖目錄V
    表目錄VIII
    第一章 緒論1
    1-1研究動機與背景1
    1-2研究方法與目的2
    1-3章節提要2
    第二章 歐規數位電視地面廣播系統4
    2-1正交分頻多工系統簡介4
    2-2DVB-T系統之規格與參數7
    2-3通道編碼技術11
    2-3-1外部通道編碼11
    2-3-1-1外部編碼器11
    2-3-1-2外部交錯器13
    2-3-2內部通道編碼14
    2-3-2-1內部編碼器14
    2-3-2-2內部交錯器15
    第三章 迴旋碼與位元交錯碼18
    3-1迴旋碼之定義18
    3-1-1編碼架構18
    3-1-2位元擷取(Punctured)技術21
    3-2Viterbi解碼之演算法23
    3-2-1硬式判決解碼-漢明距離(Hamming Distance)23
    3-2-2軟式判決解碼-歐幾里德距離(Euclidean Distance)26
    3-2-2-1位元分支路徑計量值計算[2]26
    3-2-2-2量化位元數模擬分析41
    3-3反覆式解碼46
    第四章 Viterbi解碼器之硬體架構48
    4-1設計與實現流程48
    4-1-1分支路徑計量值單元50
    4-1-2加-比較-選擇單元54
    4-1-3存活記憶體單元60
    4-2電路模擬與合成報告67
    第五章 電腦模擬與結果分析75
    5-1可加性高斯白雜訊通道75
    5-2迴旋碼用於DVB-T之系統效能77
    5-3反覆式解碼之系統效能84
    第六章 結論與未來展望86
    參考文獻87
    Reference [1]ESTI, “Digital Video Broadcasting(DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television”, European Telecommunication Standard EN300744 v1.4.1, 2001
    [2]Simplified Soft-Output Demapper for Binary Interleaved COFDM with Application to HIPERLAN/2, Filippo Tosato1, Paola Bisaglia, HPL-2001-246 October 10th , 2001
    [3]C. B. Shung, P. H. Siegel, G. Ungerboeck, and H. K. Thapar, “VLSI architectures for metric normalization in the Viterbi algorithm,”IEEE ICC, Vol. 4, pp.1723-1728, Apr.1990.
    [4]Jae-Sun Han; Tae-Jin Kim; Chanho Lee, “High performance Viterbi decoder using modified register exchange methods”, Circuits and Systems, 2004. ISCAS ’04. Proceedings of the 2004 International Symposium on Volume 3, 23-26 May 2004 Page(s):III – 553-6 Vol.3.
    [5]Biver, M.; Kaeslin, H.; Tommasini, C.,”In-place updating of path metrics in Viterbi decoders”, IEEE Journal on Solid-State Circuits, Vol 24, Issue 4, Aug. 1989 Page(s): 1158~1160.
    [6]Ivan M. Onyszchuk, “Truncational Length for Viterbi Decoding.” IEEE Trans. On Communication, Vol.COM-39, pp.1023~1026, July 1991.
    [7]D. A. F. Ei-Dib and M. I. Elmasry, “Low-power register-exchange Viterbi decoder for high-speed wireless communications” IEEE ISCAS, Vol. 5, pp. V737~740, May. 2002.
    [8]T. K. Truong, M. –T. Shih, I. S. Reed, and E. H. Satorius, “ A VLSI design for a trace-back Viterbi decoder,” IEEE Trans. on Communications, Vol. 40, No.3, pp.616~624, Mar. 1992.
    [9]Feygin, G.; Gulak, P, “Architectural tradeoffs for survivor sequence memory management in Viterbi decoder”, Communications, IEEE Trans. on Communications , Vol 41, Issue 3, March 1993 Page(s):425~429.
    Advisor
  • Yih-Ming Chen(陳逸民)
  • Files
  • 975203013.pdf
  • approve in 2 years
    Date of Submission 2010-07-27

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