Title page for 975201062


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Student Number 975201062
Author Chih-yu Yen(顏志佑)
Author's Email Address yenchihyu@hotmail.com
Statistics This thesis had been viewed 586 times. Download 1092 times.
Department Electrical Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Si Substrate Noise Coupling and Guard Ring Analysis
Date of Defense 2010-07-08
Page Count 80
Keyword
  • guard ring
  • substrate noise
  • Abstract Continuous scaling of CMOS technology has resulted in chips with digital and analog circuit integrating on the same chip. However, the performance of the analog circuits will degrade due to substrate noise generated by the digital circuits. Substrate noise is an effect that can no longer be ignored in integrated circuit design.
    This research content divides into two parts. First we proposed a novel structure as guard ring for device to suppress substrate noise by tsmc 0.18 μm CMOS technology. We applied bias to the guard ring and observed the isolation for low and high frequency. Finally we concluded the best condition for the isolation.
    The second part is substrate noise coupling effect to circuit. The effect of signal on the VCO was investigated by applied various magnitudes and frequency square signal to the substrate in term of output power and phase noise. The output power and phase noise was degraded for various magnitudes and clock frequencies of the square signal applied. Further, the suppression of the signal on the VCO by the global guard ring was demonstrated and compared for various guard ring bias schemes.
    Table of Content 摘要I
    AbstractII
    目錄III
    圖目錄V
    表目錄VIII
    第一章 緒論1
    1.1研究背景與動機1
    1.2相關研究發展4
    1.3論文架構5
    第二章 何謂基板雜訊及其傳輸機制6
    2.1簡介6
    2.2何謂基板雜訊及其來源6
    2.3基板雜訊耦合機制9
    2.3.1基板雜訊傳輸機制9
    2.3.2基板雜訊接收機制10
    2.4抑制基板雜訊方法與文獻回顧11
    第三章 基板雜訊防護環設計與量測分析14
    3.1簡介14
    3.2防護環設計與Medici模擬結果14
    3.2.1防護環設計14
    3.3防護環實際製作與量測結果23
    3.3.1防護環實際製作23
    3.3.2防護環量測結果25
    3.4基板雜訊耦合分析31
    3.5等效電路34
    3.6 結論37
    第四章 基板雜訊對射頻電壓控制振盪器之耦合影響38
    4.1 簡介38
    4.2 電壓控制振盪器架構39
    4.3 基板雜訊耦合影響測量與分析40
    4.3.1電路佈局圖40
    4.4 利用防護環抑制基板雜訊之量測結果49
    4.4.1電路佈局圖49
    4.5 結論55
    第五章 結論56
    參考文獻57
    附錄 A60
    附錄 B65
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    Advisor
  • Yue-ming Hsin(辛裕明)
  • Files
  • 975201062.pdf
  • approve in 1 year
    Date of Submission 2010-07-20

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