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Student Number 975201027
Author Ting-Ju Chen(³¯«F¦p)
Author's Email Address No Public.
Statistics This thesis had been viewed 919 times. Download 192 times.
Department Electrical Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Testing and Repair of Memories in 3D-SiP Chips
Date of Defense 2010-06-17
Page Count 103
Keyword
  • Diagnostic Data Compression
  • Memory Built-In Self-Repair
  • Memory Built-In Self-Test
  • Abstract System-in-Package (SiP) integration technology provides a good solution for integrating components with different technologies. In an SiP, typically, various types of dies are stacked and connected with bonding wires. Among those dies, memory die is one widely used die. Furthermore, different types of memory dies may be integrated in the SiP. Using external automatic test equipment (ATE) to test these memory dies in the post-packaging phase becomes very difficult, since the I/O terminals of most of these memory dies cannot be directly accessed through the I/O pins of the package. Effective test techniques for testing these memory dies in the post-packaging phase thus should be developed. Apparently, built-in self-test (BIST) technique is a good solution for testing the memory dies in SiP designs.
     In the first part of this thesis, a programmable BIST scheme is proposed to test the SRAMs in a System-on-Chip(SoC) die, Flash memory dies, and SDRAM dies in an SiP chip. For the testing of SDRAMs, an efficient test procedure is proposed to reduce the testing time. Also, a specific diagnosis approach is proposed to diagnose the SDRAM when it is tested in burst mode. The proposed BIST scheme has the advantages of high diagnosability, high portability, parallel test, and low test complexity. Experimental results show that the area overhead of the proposed BIST circuit for one 512K-bit SRAM and one 1M-bit SRAM in an SoC die, and one 256M-bit Flash die is only about 0.07%.
     In the second part of this thesis, an adaptive syndrome compression algorithm for variable-size symbols is proposed to reduce the diagnostic data exportation time and the storage requirement of ATE. Experimental results show that the area overhead of the proposed BIST circuit with the adaptive syndrome compressor for an SiP with one SoC die in which one 512K-bit SRAM and one 1M-bit SRAM are embedded, and one 256M-bit Flash memory die is only about 0.08%.
     In the third part of this thesis, a reconfigurable built in redundancy analyzer (ReBIRA) scheme which can provide the optimal repair efficiency using very low area cost and one test run is proposed. In addition, a level- based buffer is proposed to extract multiple-bit failure of a faulty word to support the at-speed test and redundancy analysis for word-oriented RAMs. Experimental results show that the area cost for implementing the proposed ReBIRA scheme is much lower than that of existing works.
    Table of Content 1 Introduction 1
    1.1 Test Flow of System-in-Package Chips 1
    1.2 Built-In Self-Repair Techniques 3
    1.3 Memory Testing Issues of SiP Chips 8
    1.4 Targeted Fault Models 9
    1.5 Thesis Motivations and Contributions 10
    1.6 Thesis Organization 13
    2 Built-In Self-Test Scheme with Diagnosis Ability for Memories in SiP Chips 14
    2.1 Proposed Programmable BIST Scheme 14
    2.1.1 Programmable BIST Architecture 14
    2.1.2 Design of the TPG 17
    2.1.3 Test Interfaces for Flash and SDRAM Testing 19
    2.2 SRAM Testing 21
    2.3 SDRAM Testing 22
    2.3.1 Speed Grading and Data Retention Test 22
    2.3.2 Testing Time Reduction Technique 22
    2.3.3 Diagnosis Feature 26
    2.4 Flash Memory Testing 27
    2.5 Interconnection Testing 28
    2.6 Experimental Results and Analysis 31
    3 Adaptive Diagnostic Syndrome Compression Scheme for RAMs 35
    3.1 Introduction to Diagnostic Syndrome Compression Scheme 35
    3.2 An Adaptive Diagnostic Syndrome Compression Scheme 37
    3.3 Experimental Results and Analysis 43
    4 Built-In Self-Repair Scheme for RAMs in SiP Chips 48
    4.1 A Built-In Redundancy-Analysis Scheme with Optimal Repair Efficiency for RAMs 48
    4.1.1 The Proposed At-Speed ReBIRA Scheme 48
    4.1.2 Design of the Proposed At-Speed ReBIRA Circuit 54
    4.1.3 Experimental Results and Analysis 65
    4.2 BISR Scheme for External DRAMs in SiP Chips 76
    4.2.1 Architecture of Address Remapping Unit for External DRAMs 77
    5 Conclusion and Future Work 79
    5.1 Conclusion 79
    5.2 Future Work 80
    Bibliography 81
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  • Jin-Fu Li(§õ¶iºÖ)
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    Date of Submission 2010-08-27

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