Title page for 975201023


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Student Number 975201023
Author Yo-hao Tu(涂祐豪)
Author's Email Address No Public.
Statistics This thesis had been viewed 646 times. Download 173 times.
Department Electrical Engineering
Year 2010
Semester 1
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title A Wide Range Delay-Locked Loop with Phase Error Calibration and Frequency Multiplier
Date of Defense 2010-10-04
Page Count 78
Keyword
  • Delay-Locked Loop (DLL)
  • Duty Cycle Corrector (DCC)
  • Frequency Multiplier (FM)
  • Half Transparent (HT)
  • Stuck Locking
  • Abstract   This study presents a wide-range and multiphase DLL-based clock generator with the Phase Error Compensation loop. For more applications, we proposed a frequency multiplier to synthesize a combined clock. In this voltage control delay line, we take the multi-gain technique to achieve the wide-range operation frequency. And we proposed a Phase Error Compensation loop with the timing amplifier. It is difficult to realize a DLL in high operation frequency, so using multiphase technique can solve this problem. And the multiphase architecture can become the clock generator of a Transmitter (Tx).
      This study was implemented by TSMC 180 nm 1P6M CMOS process. The input frequency range of the proposed DLL is from 80 MHz to 600 MHz with 12-phase output. The output range of frequency multiplier is from 0.96 GHz to 2.5 GHz. The chip area is 0.745 × 0.745 mm2 and the core area is 0.356 × 0.356 mm2. The power consumption is 19.2 mW at a supply of 1.8 V. The peak-to-peak jitter and rms jitter of delay locked loop are 21.22 ps and 2.62 ps at 800 MHz. The peak-to-peak jitter and rms jitter of frequency multiplier are 35.11 ps and 4.28 ps at 2.4 GHz. And the Phase Error Compensation loop can improve 33.33% of the static phase error.
    Table of Content Abstract .......................................................................................................................... ii
    目錄................................................................................................................................ iii
    致謝................................................................................................................................ vi
    圖目錄............................................................................................................................ vii
    表目錄............................................................................................................................ ix
    第1章 緒論..................................................................................................................... 1
    1.1 研究動機.................................................................................................................. 1
    1.2 發射端電路.............................................................................................................. 2
    1.3 論文架構.................................................................................................................. 4
    第2章 延遲鎖定迴路架構與理論................................................................................. 5
    2.1 傳統類比式延遲鎖定迴路架構.............................................................................. 5
    2.1.1 相位偵測器........................................................................................................... 6
    2.1.2 充電幫浦與迴路濾波器....................................................................................... 7
    2.1.3 電壓控制延遲線................................................................................................... 8
    2.1.3.1 電阻電容時間常數控制式延遲元件................................................................ 9
    2.1.3.2 可變電容式延遲元件[2] ................................................................................... 9
    2.1.3.3 電流限制式延遲元件[2] ................................................................................... 10
    2.1.3.4 差動對稱性負載式延遲元件............................................................................ 11
    2.2 延遲鎖定迴路之理論分析...................................................................................... 12
    2.2.1 錯誤鎖定............................................................................................................... 12
    2.2.2 鎖定範圍............................................................................................................... 13
    2.2.3 系統分析............................................................................................................... 14
    2.2.4 行為模型............................................................................................................... 15
    第3章 改良式相位偵測器與相位誤差補償迴路......................................................... 17
    3.1 介紹.......................................................................................................................... 17
    3.2 半穿透架構式相位偵測器問題探討...................................................................... 17
    3.2.1 半穿透架構式相位偵測器................................................................................... 17
    3.2.2 半穿透架構式相位偵測器的錯誤狀況............................................................... 18
    3.3 改良式相位偵測器.................................................................................................. 21
    3.3.1 改良式責任週期校正電路(MDCC) .................................................................... 21
    3.3.2 具有改良式責任週期校正電路的相位偵測器................................................... 22
    3.4 相位誤差補償.......................................................................................................... 26
    3.4.1 時間放大器........................................................................................................... 26
    3.4.2 相位誤差補償電路............................................................................................... 28
    第4章 具寬頻操作及自我相位校正之延遲鎖定迴路與頻率倍頻器......................... 31
    4.1 介紹.......................................................................................................................... 31
    4.2 電路架構與系統分析.............................................................................................. 32
    4.3 電路設計.................................................................................................................. 33
    4.3.1 充電幫浦............................................................................................................... 33
    4.3.2 電壓控制延遲線................................................................................................... 34
    4.3.3 頻率倍頻器........................................................................................................... 38
    4.3.4 跳段機制............................................................................................................... 40
    4.3.5 拴鎖鎖定保護電路............................................................................................... 42
    第5章 晶片模擬與量測................................................................................................. 45
    5.1 電路佈局.................................................................................................................. 45
    5.2 電路模擬.................................................................................................................. 46
    5.2.1 自動跳段模擬圖................................................................................................... 46
    5.2.2 多相位輸出和相位抖動模擬圖........................................................................... 48
    5.3 量測環境考量.......................................................................................................... 51
    5.4 晶片與印刷電路板照相.......................................................................................... 54
    5.5 量測結果.................................................................................................................. 55
    5.6 規格比較.................................................................................................................. 59
    第6章 結論與未來研究方向......................................................................................... 61
    6.1 結論.......................................................................................................................... 61
    6.2 未來研究方向.......................................................................................................... 61
    參考文獻........................................................................................................................ 62
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    Advisor
  • Kuo-hsing Cheng(鄭國興)
  • Files
  • 975201023.pdf
  • approve in 3 years
    Date of Submission 2010-10-19

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