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Student Number 965911003
Author Hsing-shan Ko(柯幸姍)
Author's Email Address 965911003@cc.ncu.edu.tw
Statistics This thesis had been viewed 1250 times. Download 1113 times.
Department Electrical Engineering
Year 2008
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Design of Low Phase Noise Phase-locked-loop (PLL)
Date of Defense 2009-07-30
Page Count 70
Keyword
  • jitter
  • phase noise
  • PLL
  • Abstract The chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system.
    The PLL is application to time domain it’s main performance is jitter. The PLL is application to frequency domain it’s main performance is phase noise. When phase noise is best means jitter is lower.
    In high-speed system, the circuit for very sensitive to noise. In this thesis, design of low phase noise is proposed. We analysis PLL noise source and find that main effects noise source block and noise analysis in block circuit.
    We use the TSMC 0.18 um 1P6M process with supplying 1.8V voltage in proposed PLL. The reference input frequency is 187.5MHz and the output frequency is 3GHz. The period jitter of output frequency is 3ps (pk-pk) RMS jitter is 600 fs. The power consumption of the proposed PLL is 23.7 mW at 3GHz and the Locking time of the PLL is 600ns. The core area is 0.034mm2.
    Table of Content 摘要........................................................................i
    Abstract...............................................................ii
    圖目錄................................................................... v
    表目錄.................................................................vii
    第一章 緒論........................................................ 1
    1.1 研究動機......................................................................................................................1
    1.2 論文架構......................................................................................................................2
    第二章 鎖相迴路基本觀念................................ 3
    2.1 鎖相迴路架構及操作原理..........................................................................................3
    2.1.1 相位頻率偵測器(Phase Frequency Detector, PFD) .................................4
    2.1.2 充電泵(Charge Pump, CP) ..........................................................................5
    2.1.3 迴路濾波器(Loop Filter)................................................................................8
    2.1.4 電壓控制振盪器(Voltage Control Oscillator)..............................................8
    2.2 鎖相迴路的轉移函數分析........................................................................................ 11
    第三章 鎖相迴路的雜訊分析.......................... 18
    3.1 鎖相迴路雜訊的基本分析[10] ................................................................................18
    3.1.1 電壓控制振盪器的雜訊................................................................................19
    3.1.2 輸入的雜訊....................................................................................................20
    3.2 迴路中各組件之雜訊分析[11]-[12] ........................................................................20
    3.3 電壓控制振盪器相位雜訊分析................................................................................22
    3.3.1 電壓控制振盪器之相位雜訊.......................................................................23
    3.3.2 單端環型電壓控制振盪器之相位雜訊[15].................................................24
    第四章 鎖相迴路設計流程.............................. 32
    4.1 鎖相迴路設計流程...................................................................................................32
    4.2 論文採用電壓控制振盪器之架構分析與設計.......................................................33
    4.2.1 論文採用電壓控制振盪器之架構分析.......................................................33
    4.2.2 電路設計與其模擬結果...............................................................................34
    4.3 改善架構討論與其模擬結果...................................................................................38
    4.3 鎖相迴路設計考量...................................................................................................44
    第五章 晶片實現與模擬結果.......................... 46
    5.1 鎖相迴路各組件模擬結果.......................................................................................46
    5.1.1 相位頻率偵測器(PFD).................................................................................46
    5.1.2 充電泵(CP)與迴路濾波器(LF)....................................................................48
    5.1.3 頻率除頻器(FD) ...........................................................................................49
    5.2 鎖相迴路模擬結果...................................................................................................51
    5.3 晶片佈局及電路規格比較與討論...........................................................................53
    第六章 結論....................................................... 58
    6.1 結論...........................................................................................................................58
    6.2 未來改進方向...........................................................................................................58
    參考文獻............................................................. 59
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    Advisor
  • none(鄭國興)
  • Files
  • 965911003.pdf
  • approve in 3 years
    Date of Submission 2009-07-31

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