Title page for 965302005


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Student Number 965302005
Author Shih-Ming Wang(王士銘)
Author's Email Address No Public.
Statistics This thesis had been viewed 649 times. Download 268 times.
Department Executive Master of Computer Science and Information Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Design of UDP/IP Hardware Accelerator for Gigabit Ethernet
Date of Defense 2010-07-26
Page Count 59
Keyword
  • offload engine
  • UDP offload engine
  • UDP/IP offload engine
  • Abstract In networked embedded systems. Network computing usually takes a lot of computing resources of processor. Grade and above, especially in embedded Gigabit Network System, Because of the speed and power consumption issues, It is not suitable to use embedded software to achieve in the MCU or DSP. Therefore, this research is to design a UDP / IP hardware accelerator. In order to reduce the computational overhead and improve the system overall efficiency of high-speed network. In this thesis, we use MIAT methodology to design an embedded hardware UDP / IP hardware accelerator. Which including pipelined transmitter and receiver controllers, and a connection table which can store information of current connection. Connection information can be modified by instructions inside UDP package sent by remote side, First we analysis whole system with hierarchical modular IDEF0, each module can operate independently, then we perform discrete event modeling on each module by GRAFCET. Finally we write VHDL hardware description language code to synthesis GRAFCET into hardware circuit, we complete functional verification for each module in FPGA. The whole system uses a 1404 Logic Elements, transmit speed up to 137.14 MB/s, receive is 173.10MB/s. With a commercially available Gigabit MAC and PHY for Embedded system, we experiment the integration and performance verification test. The results of this study can be used in future high-speed remote video monitoring network multimedia applications or high data flow applications online games.
    Table of Content 摘要ii
    ABSTRACTiii
    誌謝iv
    目 錄v
    第一章 緒論1
    1.1 研究動機與目標1
    1.2 文獻探討1
    1.3 論文結構3
    第二章 嵌入式UDP/IP4
    2.1 開放式系統互聯分層模型4
    2.2 TCP/IP參考模型5
    2.3 檢查碼6
    2.4 網際網路通訊協定7
    2.5 使用者資料包通訊協定9
    第三章 實作12
    3.1 IDEF012
    3.2 GRAFCET15
    3.3 VHDL合成規則18
    3.4 系統架構19
    3.3 可重新組態的連線表23
    3.4 UDP封包產生模組24
    3.5 IP封包產生模組27
    3.6 IP封包檢查模組30
    3.7 UDP封包檢查模組31
    3.8 傳送控制器的管線化控制模組33
    3.9 接收管線化控制模組35
    第四章 系統整合與驗證37
    4.1 MIAT-C3X實驗板37
    4.2 LAP-C(16128) 邏輯分析儀38
    4.3 UDP/IP硬體加速器電路合成39
    4.3.1 傳送控制器39
    4.3.2 接收控制器40
    4.4實驗結果42
    4.4.1 UDP封包產生器43
    4.4.2 IP封包產生器44
    4.4.3 UDP/IP傳送控制器45
    第五章 結論47
    參考文獻49
    Reference [1] CHEN, Ching-Han; DAI, Jia_Hong, “Design and high-level synthesis of discrete-event controller”, National Conference of Automatic Control and Mechtronics System, vol.1, pp. 610–615, 2002
    [2] 郭家銘,“模糊系統高階合成”,義守大學電機工程學系碩士學位論文,2001
    [3] 杜金鴻,“機率神經網路之系統設計與高階合成”, 義守大學電機工程學系碩士學位論文,2003
    [4] Herrmann, F.L.; Perin, G.; de Freitas, J.P.J.; Bertagnolli, R.; dos Santos Martins, J.B.; “AN UDP/IP NETWORK STACK IN FPGA”, Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on Digital Object Identifier: 10.1109/ICECS.2009.5410757, pp. 836 – 839, 2009
    [5] Nikolaos Alachiotis, Simon A. Berger,Alexandors Stamatakis, “EFFICIENT PC-FPGA COMMUNICATION OVER GIGABIT ETHERNET”, 2010
    [6] Andreas Löfgren Lucas Lodesten Stefan Sjöholm,“An analysis of FPGA-based  UDP/IP stack parallelism for embedded Ethernet connectivity,”NORCHIP Conference, 23rd, 2005
    [7] V.Vishwanath, P.Balaji, W. Feng, J. Leigh and D.K. Panda. "A Case for UDP Offload Engines in LambdaGrids," Fourth International Workshop on Protocols for Fast Long- Distance Networks (PFLDnet 2006), Nara, Japan, February 2-3, 2006
    [8] TCP/IP Protocol Suite (3rd Edition) by Behrouz A. Forouzan, Sophia Chung Fegan (ISBN:0072460601)
    [9] J. Postel, ”Internet Protocol,” RFC 791 (Standard), In-ternet Engineering Task Force, September 1981. (Up-dated by RFC 1349).
    [10] J. Postel, ”User Datagram Protocol,” RFC 768 (Stan-dard), Internet Engineering Task Force, August 1980.
    [11] Mayer, R.J.;“IDEF0 Function Modeling”, Air Fprce Systems Command, May, 1992.
    [12] Colquhoun G,J; Baines R.W;“Ageneric IDEF0 model of process planning”, Int. J. Production Research, Vol.29,No11,pp2239-2257,1991.
    [13] Zaytoon, J.; Carre-Menetrier, V.;“From discrete-event systems to hybrid systems”, IRRR Systems, Man, and Cybernetics, Vol. 1, pp159-164,1999.
    [14] David, R.;“Grafcet :A powerful tool for specification of logic controllers”, IEEE Trans on control systems technology, Vol.3, No 3, p253-268,1995.
    [15] Linkens, D.A.; Tanyi, E.B.;“Design and implementation of a hybrid modeling and simulation strategy for integrated control”, IEEE Computer-Aided Control System Design, pp 352-357,1996.
    [16] Ross, D.T.;“Applications and Extensions of SADT”, IEEE,pp.23-34,1985.
    [17] Petri, C. A., Kommunikation mit Automaten, Schriften des Rheinisch, Westfalischen Institutes fur Intrumentelle Mathematik and Der Universitat Bonn, 1962, translation bt Greene, C. F. Applied Data Research Inc., Suppl. 1 to Tech Report RADC-TR-65-337, N.Y.,1965.
    Advisor
  • Ching-Han Chen(陳慶瀚)
  • Files
  • 965302005.pdf
  • approve in 3 years
    Date of Submission 2010-07-28

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