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Student Number 965201059
Author Yu-yuan Wang(王裕淵)
Author's Email Address sldisck@msn.com
Statistics This thesis had been viewed 642 times. Download 1084 times.
Department Electrical Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Fabrication and Characterization of Germanium Quantum Dots MOSFET with Electric-field Induced Tunable Tunnel Barriers in Si3N4/SiO2/Si3N4 Stack.
Date of Defense 2010-07-26
Page Count 108
Keyword
  • E-field induced tunable tunnel barriers
  • Ge floating dot transistor
  • nonvolatile memory
  • Abstract In this thesis, we explored two wide bandgap insulators, silicon-dioxide and silicon nitride, as a stacked dielectric for forming a tunable tunnel barrier under electric-field modulation. The so-formed tunnel dielectric behaves like a symmetric quasi-triangle potential barrier, which is expected to enhance the read and write speeds for memory application. In addition, we also incorporate germanium quantum dots (QDs) to replace the floating poly-Si gate, so that a high speed and good charge retention Ge QDs flash memory is demonstrated.
      The stacked tunnel dielectric of Si3N4/SiO2/Si3N4 is produced by thermally oxidizing amorphous Si3N4 at 1050 oC and its equivalent oxide thickness (EOT) is less than 5 nm. The so-formed stacked tunnel dielectric behaves like a quasi-triangle potential barrier under E-field manipulation. Incorporating Ge QDs with the quasi-triangle tunnel barrier into the MOSFET structure, we realized a floating-dot nonvolatile memory cell transistor with the write/read voltages of +8 V and -6 V, write/read time of 1 ms and 70 μs at a threshold voltage shift (ΔVTH = 0.6 V). This Ge QDs transistor have good charge retention of 58 % after 1E8 s and excellent endurance after more than 1E6 read/write operations.
    Table of Content 目錄
    中文摘要………………………………………………i
    英文摘要………………………………………………ii
    致謝……………………………………………………iii
    目錄……………………………………………………iv
    圖目錄…………………………………………………vii
    表目錄…………………………………………………xiv
    第一章序論……………………………………………1
    1-1研究背景……………………………………………1
    1-2浮點的種類…………………………………………6
    1-3高介電係數材料的應用……………………………8
    1-4研究動機……………………………………………8
    1-5研究目的與應用……………………………………11
    第二章浮點記憶體之操作原理………………………21
    2-1前言…………………………………………………21
    2-2浮點記憶體之寫入與抹除原理……………………21
    2-3載子穿隧注入………………………………………21
    2-3-1直接穿隧機制……………………………………22
    2-3-2Fowler-Nordheim 注入機制………………………23
    2-3-3Frenkel-Poole 注入………………………………24
    2-3-4通道熱電子注入…………………………………25
    2-4元件穿隧機制討論…………………………………26
    第三章鍺浮點電晶體之製程與開發…………………32
    3-1前言…………………………………………………32
    3-2鍺奈米晶粒製作方法………………………………32
    3-3複晶矽鍺沉積在不同材料的物理性質……………33
    3-3-1前言………………………………………………33
    3-3-2沉積複晶矽鍺薄膜之潛伏期……………………33
    3-3-3複晶矽鍺沉積在二氧化矽、非晶矽以及氮化矽
         上的物理性質……………………………………34
    3-4濕氧氧化沉積在氮化矽上的複晶矽鍺層…………36
    3-5利用乾氧氧化氮化矽形成二氧化矽………………38
    3-6鍺浮點電晶體的製作流程…………………………40
    3-6-1元件隔離層的製作………………………………40
    3-6-2閘堆疊的製作……………………………………41
    3-6-3基板重摻雜………………………………………43
    3-6-4金屬電極…………………………………………43
    3-7閘堆疊層的分裂條件………………………………44
    第四章鍺浮點電晶體的電性量測與分析……………57
    4-1前言…………………………………………………57
    4-2電晶體基本電性量測………………………………58
    4-3磁滯現象量測………………………………………58
    4-4複晶矽浮閘與鍺浮點電晶體的記憶體特性量測…59
    4-4-1寫入/抹除電壓與速度量測………………………60
    4-4-2儲存時間量測……………………………………65
    4-4-3耐用性量測………………………………………68
    4-5複晶矽浮閘與鍺浮點電晶體的電性量測分析……71
    第五章總結與未來展望………………………………103
    參考文獻………………………………………………104
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    Advisor
  • Pei-wen Li(李佩雯)
  • Files
  • 965201059.pdf
  • approve in 1 year
    Date of Submission 2010-08-16

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