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Student Number 965201027
Author Hsing-Chen Lu(¿c¬P¨°)
Author's Email Address No Public.
Statistics This thesis had been viewed 934 times. Download 413 times.
Department Electrical Engineering
Year 2008
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Efficient Yield and Reliability Enhancement Techniques for Random Access Memories
Date of Defense 2009-07-07
Page Count 81
Keyword
  • Diagnostic Data Compression
  • Online Transparent Test/Repair
  • Random Access Memories
  • Abstract Yield and reliability are two key challenges for designing nano-scale chips. Embedded memory is one key component in modern system-on-chip (SoC) designs. It typically represents a significant portion of the chip area as well. Moreover, it is designed with the smallest transistors and aggressive design rules. Thus, the yield and reliability of embedded memories dominate that of SoCs. Therefore, efficient yield and reliability enhancement techniques for embedded memories are very important for SoCs.
    Built-in self-diagnosis (BISD) and built-in self-repair(BISR) are two key techniques for improving the yield of embedded memories. Typically, a BISD design exports diagnostic data serially. In the first part of this thesis, a diagnostic data compression technique is proposed to reduce the diagnostic data of a RAM with error correction code (ECC). By reusing the ECC circuit, the proposed approach can compress the diagnostic data efficiently with very low area cost.
    In the second part of this thesis, a transparent BISR scheme for RAMs with ECC is proposed to enhance the yield and reliability of RAMs. The transparent BISR scheme can perform off-line test/repair for RAMs in production phase. It also can perform online test/repair for RAMs in operation. In online test/repair mode, the transparent BISR scheme performs transparent march tests for the RAM under test and repairs the RAM cells with hard faults if some spares are unused after the off-line test/repair phase. This can prolong the reliability of the RAM. In comparison with existing transparent test approaches, the proposed transparent test approach has the following advantages: fault-location capability and low test complexity. Experimental results show that the area cost of the proposed transparent BISR scheme for RAMs with ECC is low¡Xonly about 4.8% for a 4K¡Ñ39-bit SRAM.
    In the third part of this thesis, a shared transparent test and repair scheme for multiple homogeneous RAMs without ECC is proposed to reduce the area cost. In the shared transparent test and repair scheme, a shared code memory is designed to store the signature of a RAM under test. Thus, the RAMs sharing the code memory are tested and repaired one by one in a time-multiplexing method. Since the code memory is shared by multiple homogeneous RAMs, the area cost of the transparent test and repair scheme is reduced. In comparison with typical transparent BIST schemes, the proposed scheme has good fault location capability. The signature prediction phase is only 1N for an N¡ÑB-bit RAM.
    Table of Content Contents
    1 Introduction 1
    1.1 Yield-Enhancement Techniques for RAMs 1
    1.1.1 Built-In Self-Test and Built-In Self-Diagnosis Techniques 1
    1.1.2 Built-In Self-Repair Techniques 3
    1.2 Reliability Enhancement Techniques for RAMs 6
    1.2.1 Error Correction Code Techniques 6
    1.2.2 Periodic Transparent Test Techniques 9
    1.3 Thesis Contribution 12
    1.4 Thesis Organization 13
    2 Diagnosis of RAMs with ECC using Syndrome Compression 14
    2.1 Review of Diagnostic Data Compression Schemes 14
    2.2 Syndrome Compression Scheme by Reusing ECC Encoder 15
    2.2.1 Overview of Proposed Syndrome Compression Scheme 15
    2.2.2 BISD mplementation 18
    2.3 Evaluation and Analysis 20
    2.3.1 Compression Ratio and Re-construction Ratio Evaluation 20
    2.3.2 Hardware Overhead 24
    2.3.3 Comparison and Summary 27
    3 Transparent Test and Repair Techniques for RAMs with ECC 30
    3.1 Programmable Online/Off-line Built-In Self-Test Scheme for RAMs with ECC 31
    3.2 Programmable Online/Off-line Built-In Self-Repair Scheme for RAMs with ECC 34
    3.3 Experimental Results and Analysis 41
    3.3.1 Reliability Evaluation 41
    3.3.2 Hardware Overhead and Yield Improvement 50
    3.3.3 Comparison and Summary 54
    4 Transparent Test/Repair Schemes for Homogeneous RAMs in Multi-Core Chips 56
    4.1 Transparent Test/Repair Schemes for Homogeneous RAMs 56
    4.2 In-Field Diagnosis and Repair Scheme for RAMs using Wireless Test Platform 65
    4.3 Experimental Results and Analysis 68
    4.3.1 Hardware Overhead 68
    4.3.2 Comparison and Summary 69
    5 Conclusions and Future Work 72
    5.1 Conclusions 72
    5.2 Future Work 73
    Bibliography 74
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    Advisor
  • Jin-Fu Li(§õ¶iºÖ)
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    Date of Submission 2009-08-30

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