Student Number 955201106 Author Chun-Hsiang Yeh(葉竣翔) Author's Email Address No Public. Statistics This thesis had been viewed 1041 times. Download 11 times. Department Electrical Engineering Year 2007 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Title Automatic Layout Synthesis of Array-type MiM Capacitors Date of Defense 2008-07-07 Page Count 42 Keyword Automatic Layout Spatial Correlation Abstract As semiconductor technology continues to shrink, the problem of process variation is inevitable. The parameter variations should have certain spatial correlations during IC manufacturing process because all of devices are made from the common physical process. It is the closer the less for the spatial correlation of two devices. In analog-circuit layout automation, it is to determine the best layout placement of devices by considering spatial correlation and decide, in turn, the routing styles for improving the matching of desired parameters. In this thesis, two routing styles, via-less channel routing (VLCR) and balanced-via channel routing (BVCR), are proposed for completing the layout design. An example of array-type MiM capacitors is used to demonstrate the performance of the proposed channel router. In the experiment, the cases of different capacitance ratios in different segment units are considered and the evaluation of post-simulation is performed by SPICE conjunction with the parasitic parameter extractor Calibre. From the result, it is observed that routing might contribute extra up to 5 percent of mismatch after the placement determined. Routing results in the great effect on the desired performance. Table of Content 摘要i
2.2.1. 製程偏移(Process Biases) 9
2.2.2. 繞線寄生(Parasitic Interconnect) 10
3.1.1 共質心(Common-Centroid) 15
3.1.2 空間相關(Spatial Correlation) 18
3.2.1 Via-Less Channel Routing (VLCR) 26
3.2.2 Balanced-Via Chanel Routing (BVCR) 29
第四章 實驗結果 31
4.1 實驗流程 31
4.2 模擬結果 35
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Advisor Jwu-E Chen(陳竹一)
955201106.pdf Date of Submission 2008-07-18