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Student Number	955201029
Author	I-CHING TSAI(蔡宜青)
Author's Email Address	955201029@cc.ncu.edu.tw
Statistics	This thesis had been viewed 1091 times. Download 437 times.
Department	Electrical Engineering
Year	2007
Semester	2
Degree	Master
Type of Document	Master's Thesis
Language	zh-TW.Big5 Chinese
Title	A Boundary-less Design Centering Approach Using Statistical Yield Analysis Results for PLL Circuits
Date of Defense	2008-07-08
Page Count	86
Keyword	design centering yield behavioral model PLL Monte-Carlo Analysis
Abstract	With the shrinking device size in deep submicron process, the process variation influence on circuit performance is more and more serious, especially for analog circuits. Therefore, design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have become popular research directions in recent years. The main concept of DFM and DFY is to consider the process variation effects in early stage of IC designs. If we can evaluate the impacts of circuit performance under process variations in advance, the circuit yield could be improved at early stages to reduce the re-design cycles and re-spin cost. Design centering is one of the popular techniques for yield enhancement. Using the nominal design as an initial point, this technique gradually moves the nominal point toward better yield by using the results of circuit performance analysis so that most of simulation samples under process variations will locate in acceptable design regions. However, traditional design centering approaches often require complicated formulas and numerous design constrains to find out the boundaries of acceptable design regions. For complicated analog circuits, such approaches may be difficult to figure out the borders of feasible regions for yield enhancement. In this thesis, a boundary-less design centering approach is proposed for phase- locked-loop (PLL) circuits, which are very sensitive to process variations. Instead of finding the borders of feasible regions, this work searches the moving tracks of nominal points by reusing the yield analysis results and some mechanics models. After finding the nominal point with better yield, the original design will be adjusted hierarchically to match that nominal point and generate a highly-reliable circuit. Because the proposed yield enhancement approach does not need the complex process to find the boundaries of feasible regions, complicated analog circuits like PLL can also be handled efficiently. As demonstrated in the experimental results, this work indeed improves the design yield of a PLL in a short time even though the PLL circuit is so complicated.
Table of Content	第 1 章 緒 論1 1.1 研究動機1 1.2 良率分析方法3 1.3 良率最佳化與設計中心化4 1.3.1 設計中心化簡介4 1.3.2 以公式為基礎的方法5 1.3.3 以模擬為基礎的方法6 1.4 問題描述9 1.5 論文組織10 第 2 章 以行為模型為基礎的良率提升流程11 2.1 電路行為模型設計11 2.2 階層式良率分析方法17 2.3 階層式提升良率設計流程21 2.3.1 主要設計流程23 2.3.2 良率提升流程24 第 3 章 標稱設計移動法27 3.1 標稱設計移動法簡介27 3.2 移動流程30 3.2.1 通過/未通過樣本分群31 3.2.2 通過/未通過樣本質心定義32 3.2.3 力學功能定理應用36 3.2.4 標稱設計移動求值38 3.2.5 範例40 3.3 低通濾波器實驗43 3.3.1 電路架構與規格描述43 3.3.2 模擬結果45 第 4 章 行為階層參數調整與快速良率分析50 4.1 行為階層參數調整50 4.1.1 主成分分析52 4.1.2 反應曲面法53 4.1.3 雙階層參數調整法55 4.1.4 快速良率分析56 4.2 元件階層參數調整58 4.2.1 電壓控制震盪器(VCO)59 4.2.2 電荷幫浦(CP)與迴路濾波器(LF)61 4.2.3 其他數位區塊63 第 5 章 模擬結果與分析64 5.1 電路架構與規格描述64 5.2 實驗環境設定65 5.3 標稱設計移動結果66 5.4 階層式參數調整67 5.5 良率提升導向設計結果68 第 6 章 結 論72 參考資料73
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Advisor	Chien-Nan Jimmy Liu(劉建男)
Files	955201029.pdf approve immediately
Date of Submission	2008-07-12

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