Title page for 945901004


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Student Number 945901004
Author Fang-Ying Su(蘇芳瑩)
Author's Email Address No Public.
Statistics This thesis had been viewed 1978 times. Download 790 times.
Department Electrical Engineering
Year 2007
Semester 1
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title An Improved Pulse Shrinking Delay Element for Clock Jitter Measurement
Date of Defense 2008-01-14
Page Count 77
Keyword
  • jitter measurement
  • process compensation
  • pulse shrinking
  • voltage compensation
  • Abstract As the improvement of semiconductor technology, the current trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system synchronization clock signal must be accurate. We usually choose Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) as the reference clock generator. However, the jitter characteristic of the PLLs or DLLs is the most important parameter. In the past, the jitter was measured by the external equipment. But, with the increased operating frequency, it has a higher cost on jitter measuring by external equipments. Moreover, sometimes probes of external equipments will induce noise, then the measurement result is disturbed. In view the problem, the built-in jitter measurement circuit is adapted to the PLLs.
      In this thesis, an improved pulse shrinking delay element for clock jitter measurement is proposed. The traditional cyclic CMOS time-to-digital converter circuit [1] was changed the size of inverters to complete pulse shrink. We use two path with differential rising time and falling time to achieve pulse shrink. In order to make the measurable circuit have high accuracy, the compensated circuit is added to compensate the voltage and process variation. 
       The proposed circuit is designed in CMOS 0.18um 1P6M process. The operation voltage is 1.8V in the circuit. The reference frequency is 1GHz and the resolution of measurement circuit is 5ps. The power consumption is 1.7mW
    at 1GHz. Area with I/O pad in the chip is 753um × 592um, and the area of core circuit is 108um × 59um.
    Table of Content 摘要 i
    Abstract ii
    目錄 iv
    圖目錄 vii
    表目錄 x
    第一章 緒論 1
    1.1 研究動機 1
    1.2 論文架構 2
    第二章 時脈抖動定義 3
    2.1 時脈抖動定義 3
    2.2 時脈抖動分佈圖(Jitter Histogram) 4
    2.3 時脈抖動類別 6
    2.3.1 相對週期時脈抖動(Cycle-to-Cycle Jitter) 6
    2.3.2 週期時脈抖動(Period Jitter) 6
    2.3.3 長期的時脈抖動(Long-Term Jitter) 7
    第三章 時脈抖動量測方法介紹 9
    3.1 傳統Off-Chip時脈抖動量測方法 9
    3.2 On-Chip時脈抖動量測方法 10
    3.3 On-Chip時脈抖動量測相關研究 11
    3.3.1 時間數位轉換器(Time-to-Digital Converter) 11
    3.3.2 延遲串列式量測法(Delay Chain Method) 12
    3.3.3 游標尺延遲線量測法(Vernier Delay Line Method) 14
    3.3.4 改良式游標尺延遲線量測法 15
    3.3.5 游標尺振盪器量測法(Vernier Ring Oscillator Method)16
    3.3.6 DLL內插式量測法 (DLL Interpolation Method) 17
    3.3.7 時間放大器量測法(Time Amplifier Method) 19
    3.3.8 脈衝縮減量測法(Pulse Shrinking Method) 20
    3.3.9 時脈抖動量測方法比較 21
    第四章 改良式脈衝縮減元件之內建自我測試電路 22
    4.1 基本動作原理說明 22
    4.2 脈衝縮減原理 24
    4.2.1 上升時間與下降時間推演 24
    4.2.2 傳統脈衝縮減元件 25
    4.2.3 改良式脈衝縮減元件 27
    4.3 改良式脈衝縮減電路之補償電路 29
    4.3.1 電壓抖動補償電路(Voltage Compensated Circuit) 30
    4.3.2 製程變異補償電路(Process Compensated Circuit) 31
    4.4 改良式脈衝縮減電路之計數器電路 32
    4.5 系統校正與量測 34
    4.5.1 量測前之系統校正 34
    4.5.2 實際量測操作 36
    4.6 改良式脈衝縮減電路之總電路架構 36
    第五章 晶片實現與模擬 38
    5.1 設計流程介紹 38
    5.2 脈衝縮減電路之延遲線模擬 39
    5.2.1 以反相器組成之延遲線 39
    5.2.2 以NAND閘組成之延遲線 41
    5.3 傳統循環式脈衝縮減電路 42
    5.3.1 以反相器組成之延遲線電路 42
    5.3.2 以NAND閘組成之延遲線電路 44
    5.4 改良式循環脈衝縮減電路 46
    5.4.1 電壓抖動補償 47
    5.4.2 製程變異抖動補償 50
    5.5 計數器電路 52
    5.6 解析度與精確度 53
    5.6.1 解析度模擬分析 53
    5.6.2 精確度模擬分析 54
    5.6.3 抖動訊號分佈 55
    5.7 電路規格與比較表 56
    5.8 全電路佈局 57
    5.9 量測考量 58
    第六章 結論 60
    6.1 結論 60
    6.2 未來改進的方向 60
    參考文獻 62
    Reference [1] Poki Chen, and Shen-Iuan Liu, “A Cyclic CMOS Time-to Digital Converter with Deep Sub-Nanosecond Resolution,”IEEE Custom Integrated Circuits Conference, pp. 605-608, May 1999.
    [2] F. Azais, M. Renovell, Y. Bertrand, A. Ivanova, and S. Tabatabaei, “A Unified Digital Test Technique for PLLs: Catastrophic Faults Covered,” Proc. of Int. Mixed Signal Testing Workshop, pp. 269-292, June 1999.
    [3] K.A. Taylor, B. Nelson, A. Chong, H Lin, E. Chan, M. Soma, H. Haggag, J. Huard, J. Braatz, “Special Issue on BIT CMOS Built-In Test Architecture for High-Speed Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, vol.54, no.3, pp. 975-987, June 2005.
    [4] C.C. Tsai, ”On-Chip Jitter Measurement for Phase Locked Loop,” MS. Thesis, National Chiao Tung University, Institute of Electronics Engineering, Taiwan, 2002.
    [5] Antonio H. Chan and Gordon W. Roberts, “A Jitter Characterization System Using a Component-Invariant Vernier Delay Line,” IEEE Transactions on VLSI Systems, vol.12, pp. 79-95, Jan. 2004.
    [6] Bozena Kaminska, “BIST Means More Measurement Options for Designers,” EDN Magazine, Dec. 2000.
    [7] Tian Xia, Jien-Chung Lo, “Time-to-Voltage Converter for On-Chip Jitter Measurement,” IEEE Trans. on Instrumentation and Measurement, pp. 1738-1748, Dec. 2003.
    [8] A. H. Chan and G.W. Roberts, “A Synthesizable, Fast and High-Resolution Timing Measurement Device Using a Component-Invariant Vernier Delay line,” Proc. of Int. Test Conf., pp. 858-867, Nov 2001.
    [9] P.Dudek, S. Szczepanski, J. Hatfield, ” A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, vol.35, pp. 240-247, Feb. 2000.
    [10] A. H. Chan and G.W. Roberts “A Deep Sub-Micron Timing Measurement Circuit Using a Single-Stage Vernier Delay Line,” Proc. IEEE CICC, pp. 77-80, May 2002.
    [11] M.A. Abas, G. Russell, and D.J. Kinniment, “Design of Sub-10-Picoseconds On-Chip Time Measurement Circuit,” Design, Automation and Test in Europe Conference and Exhibition, vol.2, pp. 804-809, Feb. 2004.
    [12] Poki Chen, and Shen-Iuan Liu, Jingshown Wu, “A Low Power High Accuracy CMOS Time-to-Digital Converter,” IEEE Proceeding of ISCAS, pp. 281-284, 1997.
    [13] P.Chen, Shen-Luan Liu, Jingshown Wu, “A CMOS Pulse-Shrinking Delay Element for Time Interval Measurement,” IEEE J. Solid-State Circuits , vol.47, pp. 954-958, Sept. 2000.
    [14] M. Mansuri, C.K. Yang, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation,” IEEE J. Solid-State Circuits, vol.38, pp. 1804-1812, Nov. 2003.
    [15] Poki Chen “The Design and Realization of Highly Accurate CMOS Time-to-Digital Converters,” pp. 37-39.
    [16] Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang, “Self-Sampled Vernier Delay Line for Built-In Clock Jitter Measurement,” IEEE International Symposium on Circuits and Systems, ISCAS, pp.1591-1594 , May 2006.
    [17] Tian Xia, Hao Zheng, Jing Li, Ginawi, A. ,“Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.218-223, May 2005. 
    [18] J.P. Jansson, A. Mantyniemi, J. Kostamovaara, “A CMOS Time-to-Digital Converter with Better Than 10 ps Single-Shot Precision,” IEEE Journal of Solid-State Circuits, vol.41, pp.1286-1296, June 2006.
    [19] M.A. Abas, G. Russell, D.J. Kinniment, “Embedded High-Resolution Delay Measurement System Using Time Amplification”, Computers & Digital Techniques, IET, vol.1, pp. 77-86, March 2007.
    Advisor
  • Kuo-Hsing Cheng(鄭國興)
  • Files
  • 945901004.pdf
  • approve in 2 years
    Date of Submission 2008-01-23

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