Title page for 945401022


[Back to Results | New Search]

Student Number 945401022
Author Chin-Cheng Kuo(³¢®Ê¸Û)
Author's Email Address casey@ee.ncu.edu.tw
Statistics This thesis had been viewed 1516 times. Download 658 times.
Department Electrical Engineering
Year 2008
Semester 2
Degree Ph.D.
Type of Document Doctoral Dissertation
Language English
Title Bottom-up PLL Behavioral Modeling for Supply Noise Interactions and Yield Enhancement
Date of Defense 2009-06-26
Page Count 116
Keyword
  • analog behavioral model
  • PLL
  • supply noise interactions
  • yield enhancement
  • Abstract While CMOS sizes are shrinking rapidly, more and more ASIC applications adopt System-on-Chip (SOC) designs with nanometer technologies. Such analog/mixed-signal (AMS) designs with over million components lead serious integration issues during system verification. Moreover, in real environment, variations on device parameters and supply voltage can strongly influence the circuit performances and design yield, especially for sensitive analog designs. Therefore, design-for-yield (DFY) techniques have recently become popular researches to solve the yield loss issues before manufacturing. Evaluating the variation effects on analog circuit performances at early design stages can help designers improve the design yield and reduce re-design cycles and re-spin cost.
      A novel extraction flow is presented first in this dissertation to generate accurate behavioral models for PLL designs. Such bottom-up PLL model is accurate enough to replace the existing PLL intellectual property (IP) for system verification. For supply noise issues in AMS systems, a supply-noise-aware behavioral model is proposed in this dissertation to reflect real-time supply noise effects on PLL performances. Moreover, a simple SCORE (state-controlled-resistors) macromodel for PLLs is also proposed to handle the noise interaction issues at high level. Combined with the noise-aware models, this approach can provide accurate results as in real system simulation.
    Considering device parameter variations, Behavioral Monte Carlo Simulation (BMCS) approach is presented in the third part of this dissertation to estimate the design yield of a PLL efficiently. If the analyzed yield is not satisfied, a novel yield enhancement algorithm is also proposed to improve the nominal design at behavioral level. This approach can be combined with current sizing tools to enable a DFY flow for analog circuits.
      The experimental results show that accurate PLL behavioral models and related applications indeed speed up the AMS system verification. Variations in real environment can be reflected on PLL performances efficiently and considered at early design stages. We believe that these approaches can help analog designers overcome the design challenges with deep-submicron technologies.
    Table of Content Chapter 1 Introduction
    1.1Analog/Mixed-signal Systems1
    1.1.1Integration Issues3
    1.1.2Bottom-up Behavioral Modeling Approach5
    1.2Variation Influences on Analog Performances7
    1.2.1Behavioral Modeling for Supply Noise Issues10
    1.2.2Behavioral Modeling for Process Variations11
    1.2.3Yield Enhancement with Behavioral Models12
    1.3Organization13
    Chapter 2 Bottom-up PLL Behavioral Modeling
    2.1Special Characterization Mode14
    2.1.1PFD & FD15
    2.1.2CP & LF16
    2.1.3VCO17
    2.2Behavioral Model Accuracy18
    2.3Summary22
    Chapter 3 Supply Noise Interaction Aware Models
    3.1Previous Works23
    3.2Proposed Supply-noise-aware PLL Model26
    3.2.1Characterization for VCB Equations27
    3.2.2VCB for Digital Timing Parameters27
    3.2.3VCB for CP28
    3.2.4VCB for VCO29
    3.3SCORE Macromodel for PLL Circuits31
    3.3.1Ideas for the SCORE Macromodel32
    3.3.2SCORE Extraction34
    3.3.3Recursive Platform for System Verification36
    3.4Experiments37
    3.4.1Extraction for SCORE Macromodel39
    3.4.2Comparisons of Supply Noise waveforms40
    3.4.3Comparisons of PLL Responses under Noise42
    3.5Summary43
    Chapter 4 Process Variation Aware Models
    4.1Previous Works44
    4.2Hierarchical Statistical Analysis47
    4.2.1Device Level to Intermediate Level47
    4.2.2Intermediate Level to System Level49
    4.3Proposed Process-variation-aware Model52
    4.3.1Sensitivity Analysis (SA)52
    4.3.2Quasi-SA54
    4.4Experiments62
    4.5Summary68
    Chapter 5 Yield Enhancement at Behavioral Level
    5.1Previous Works69
    5.1.1Yield Analysis in Traditional Design Flow72
    5.1.2Common Design Centering Approaches74
    5.2Nominal Point Moving75
    5.3Behavioral-level Sizing & FBMCS78
    5.4Experiments82
    5.4.1Yield Enhancement for a RC LPF82
    5.4.2Yield Enhancement for a PLL85
    5.5Summary88
    Chapter 6 Conclusions and Future Works89
    Reference 91
    Reference [1]M. Narayan, ¡§Reducing Risk in Complex System Development,¡¨ http://techon.nikkeibp.co.jp/article/HONSHI/20061128/124595/
    [2]C. Guardiani, M. Bertoietti, N. Dragone, M. Malcotti, and P. McNamara, ¡§An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization,¡¨ in Proc. Design Automation Conf., pp. 760-761, Jun. 2005.
    [3]WiCkeDTM, http://www.muneda.com/Applications_DFM-DFY-Technology
    [4]M. Oishi, ¡§Technology Analysis: EDA Tools for Analog Design Slash Development Time,¡¨ http://techon.nikkeibp.co.jp/NEA/archive/200310/269245/
    [5]C.-C Kuo, ¡§Supply Noise Aware Behavioral Modeling for Phase-Locked Loop Circuits,¡¨ Master Thesis, Dept. Elec. Eng., National Central University, Taiwan, Jun., 2005.
    [6]C.-C. Kuo, Y.-C. Wang, and C.-N. J. Liu, ¡§An Efficient Approach to Build Accurate PLL Behavioral Models of PLL Designs,¡¨ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E89-A, no. 2, pp. 391-398, Feb. 2006.
    [7]A. Mounir, A. Mostafa, and M. Fikry, ¡§Automatic Behavioural Model Calibration for Efficient PLL System Verification,¡¨ in Proc. Design, Automation and Test in Europe, pp. 280-285, Mar. 2003.
    [8]M. Hinz, I. Konenkamp, and E.-H. Horneber, ¡§Behavioral Modeling and Simulation of Phase-Locked Loops for RF Front Ends,¡¨ in Proc. Midwest Symp. Circuits and Systems, pp. 194-197, Aug. 2000.
    [9]B. De Smedt and G. Gielen, ¡§Models for Systematic Design and Verification of Frequency Synthesizers,¡¨ IEEE Trans. on Circuits and Systems II, Analog Digital Signal Processing, vol. 46, no. 10, pp. 1301-1308, Oct. 1999.
    [10]W.-H. Cheng, C.-C. Kuo, P.-J. Chen, Y.-M. Wang, and C.-N. J. Liu, ¡§An Efficient Bottom-Up Extraction Approach to Build the Behavioral Model of Switched-Capacitor Sigma-Delta Modulator,¡¨ in Proc. Behavioral Modeling Simulation Conf., pp. 17-21, Sep. 2007.
    [11]S. R. Nassif, K. Bernstein, D. J. Frank, A. Gattiker, W. Haensch, B. L. Ji, E. Nowak, D. Pearson, and N. J. Rohrer, ¡§High Performance CMOS Variability in the 65nm Regime and Beyond,¡¨ in Proc. Int. Electron Devices Meeting, pp. 569-572, Dec. 2007.
    [12]A. Sarker, ¡§A Methodology for IC Power Grid Design,¡¨ in EE Times, Design News, Mar. 2005. http://www.eetimes.com/news/design/159401682 
    [13]K. J. Kuhn, ¡§Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS,¡¨ in Proc. Int. Electron Devices Meeting, pp. 471-474, Dec. 2007.
    [14]P. A. Stolk, F. P. Widdershoven, and D. B. M. Klaassen, ¡§Modeling Statistical Dopant Fluctuations in MOS Transistors,¡¨ IEEE Trans. on Electron Devices, vol. 45, no. 9, pp. 1960-1971, Sep. 1998.
    [15]Z. Wang, R. Murgai, and J. Roychowdhury, ¡§ADAMIN: Automated, Accurate Macro -modeling of Digital Aggressors for Power and Ground Supply Noise Prediction,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 1, pp. 56-64, Jan. 2005.
    [16]Y. Ogasahara, T. Enami, M. Hashimoto, T. Sato, and T. Onoye, ¡§Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement,¡¨ IEEE Trans. on Circuits and Systems II, Exp. Briefs, vol. 54, no. 10, pp. 868-872, Oct. 2007.
    [17]K. L. Wong, T. Rahal-Arabi, M. Ma, and G. Taylor, ¡§Enhancing Microprocessor Immunity to Power-Supply Noise with Clock-Data Compensation,¡¨ IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 749-758, Apr. 2006.
    [18]M. Pude, C. Washburn, P. R. Mukund, K. Abe, and Y. Nishi, ¡§An Analytical Propagation Delay Model with Power Supply Noise Effects,¡¨ in Proc. Int. Symp. Circuits and Systems, pp. 21-24, May 2006.
    [19]M. Hashimoto, J. Yamaguchi, T. Sato, and H. Onodera, ¡§Timing Analysis Considering Temporal Supply Voltage Fluctuation,¡¨ in Proc. Asia South Pacific Design Automation Conf., pp. 1098-1101, Jan. 2005.
    [20]H. Harizi, R. Haussler, M. Olbrich, and E. Barke, ¡§Efficient Modeling Techniques for Dynamic Voltage Drop Analysis,¡¨ in Proc. Design Automation Conf., pp. 706-711, Jun. 2007.
    [21]A. Muramatsu, M. Hashimoto, and H. Onodera, ¡§Effects of On-Chip Inductance on Power Distribution Grid,¡¨ IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88-A, no. 12, pp. 3564-3572, Dec. 2005.
    [22]A. Bogliolo, L. Benini, G. De Micheli, and B. Riccò, ¡§Gate-Level Power and Current Simulation of CMOS Integrated Circuits,¡¨ IEEE Trans. on VLSI Systems, vol. 5, no. 4, pp. 473-488, Dec. 1997.
    [23]H. H. Chen and D. D. Ling, ¡§Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design,¡¨ in Proc. Design Automation Conf., pp. 638-643, Jun. 1997.
    [24]R. Panda, D. Blaauw, R. Chandhry, V. Zolotov, B. Young, and R. Ramaraju, ¡§Model and Analysis for Combined Package and On-Chip Power Grid Simulation,¡¨ in Proc. Int. Symp. Low Power Electronics and Design, pp. 179-184, Jul. 2000.
    [25]H. H. Y. Chan and Z. Zilic, ¡§Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops,¡¨ in Proc. Design Automation Conf., pp. 430-435, Jun. 2007.
    [26]A. Fakhfakh, N. Milet-Lewis, J. Tomas, and H. Levi, ¡§Behavioural Modelling of Phase Noise and Jitter in Voltage-Controlled Oscillators with VHDL-AMS,¡¨ in Proc. Int. Conf. Circuits and Syst. Commun., pp. 370-373, Jun. 2002.
    [27]L. Yang, C. Wakayama, and C.-J. R. Shi, ¡§Noise Aware Behavioral Modeling of the S-D Fractional-N Frequency Synthesizer,¡¨ in Proc. Great Lakes Symp. VLSI, pp. 286-290, Apr. 2005.
    [28]F. Herzel and B. Razavi, ¡§A Study of Oscillator Jitter due to Supply and Substrate Noise,¡¨ IEEE Trans. on Circuits and Systems II, Exp. Briefs, vol. 6, no. 1, pp. 56-62, Jan. 1999.
    [29]P. Heydari and M. Pedram, ¡§Analysis of Jitter due to Power-Supply Noise in Phase-Locked Loops,¡¨ in Proc. Custom Integrated Circuits Conf., pp. 483-446, May 2000.
    [30]N. Barton, D. Ozis, T. Fiez, and K. Mayaram, ¡§The Effect of Supply and Substrate Noise on Jitter in Ring Oscillators,¡¨ in Proc. Custom Integrated Circuits Conf., pp. 505-508, May 2001.
    [31]T. Pialis and K. Phang, ¡§Analysis of Timing Jitter in Ring Oscillators due to Power Supply Noise,¡¨ in Proc. Int. Symp. Circuits and Systems, vol. 1, pp. 685-688, May 2003.
    [32]A. Demir, A. Mehrotra, and J. Roychowdhury, ¡§Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterization,¡¨ IEEE Trans. on Circuits and Systems I, Fundamental Theory and Applications, vol. 47, no. 5, pp. 655-674, May 2000.
    [33]X. Lai and J. Roychowdhury, ¡§Fast, Accurate Prediction of PLL Jitter Induced by Power Grid Noise,¡¨ in Proc. Custom Integrated Circuits Conf., pp.121-124, Oct. 2004.
    [34]X. Lai, Y. Wan, and J. Roychowdhury, ¡§Fast PLL Simulation Using Nonlinear VCO Macromodels for Accurate Prediction of Jitter and Cycle-Slipping due to Loop Nonidealities and Supply Noise,¡¨ in Proc. Asia South Pacific Design Automation Conf., pp. 459-464, Jan. 2005.
    [35]E. Salman, E. G. Friedman, and R. M. Secareanu, ¡§Substrate and Ground Noise Interactions in Mixed-Signal Circuits,¡¨ in Proc. Int. SOC Conf., pp. 293-296, Sep. 2006.
    [36]C.-C. Kuo and C.-N. J. Liu, ¡§On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems,¡¨ in Proc. IFIP Int. Conf. Very Large Scale Integration, pp. 116-121, Oct. 2006.
    [37]C.-C. Kuo and C.-N. J. Liu, ¡§Fast and Accurate Analysis of Supply Noise Effects in PLL with Noise Interactions,¡¨ accepted to appear in IEEE Trans. on Circuits and Systems I, Reg. Papers.
    [38]B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, New York: IEEE Press, 1996.
    [39]M. Mansuri and C.-K. K. Yang, ¡§A Low-Power Adaptive Bandwidth PLL and Clock Buffer with Supply-Noise Compensation,¡¨ IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804-1812, Nov. 2003.
    [40]G. Bai, S. Bobba, and I. N. Hjj, ¡§Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits,¡¨ in Proc. Design Automation Conf., pp. 295-300, Jun. 2001.
    [41]R. A. Menke, ¡§Laboratory Measurement of Voltage Drop at an Integrated Circuit Core due to Parasitic Inductances,¡¨ in Int. Symp. Electromagnetic Compatibility, pp. 921-926, Aug. 2005.
    [42]X. Lu, Z. Li, W. Qiu, D. M. H. Walker, and W. Shi, ¡§PARADE: PARAmetric Delay Evaluation under Process Variation,¡¨ in Proc. Int. Symp. Quality Electronic Design, pp. 276-280, Mar. 2004.
    [43]H. Chang and S.S. Sapatnekar, ¡§Statistical Timing Analysis under Spatial Correlations,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467-1482, Sep. 2005.
    [44]L. Guerra e Silva, Z. Zhu, J. R. Phillips, and L. Miguel Silveira, ¡§Variation-Aware, Library Compatible Delay Modeling Strategy,¡¨ in Proc. IFIP Int. Conf. VLSI, pp. 122-127, Oct. 2006.
    [45]H. Wang and T. Kuo, ¡§An Automatic Coefficient Design Methodology for High-Order Bandpass Sigma-Delta Modulator with Single-Stage Structure,¡¨ IEEE Trans. on Circuits and Systems II, Exp. Briefs, vol. 53, no. 7, pp. 580-584, Jul. 2006.
    [46]H. Tang, ¡§Symbolic Statistical Analysis of SNR Variation for Delta¡VSigma Modulators,¡¨ IEEE Trans. on Circuits and Systems II, Exp. Briefs, vol. 54, no. 8, pp. 720-724, Aug. 2007.
    [47]E. Felt, S. Zanella, C. Guardiani, and A. Sangiovanni-Vincentelli, ¡§Hierarchical Statistical Characterization of Mixed-Signal Circuits Using Behavioral Modeling,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 374-380, Nov. 1996.
    [48]J. F. Swidzinski, D. Alexander, M. Qu, and M. A. Styblinski, ¡§A Systematic Approach to Statistical Simulation of Complex Analog Integrated Circuits,¡¨ in Proc. Int. Workshop Statistical Metrology, pp. 86-89, Jun. 1997.
    [49]J. F. Swidzinski, M. A. Styblinski, and G. Xu, ¡§Statistical Behavioral Modeling of Integrated Circuits,¡¨ in Proc. Int. Symp. Circuits and Systems, pp. 98-101, May 1998.
    [50]T. Fujita, K. Okada, H. Fujita, H. Onodera, and K. Tamaru, ¡§A Method For Linking Process-Level Variability to System Performance,¡¨ in Proc. Asia South Pacific Design Automation Conf., pp. 547-551, Jan. 2000.
    [51]X. Li, J. Le, L. T. Pileggi, and A. Strojwas, ¡§Projection-Based Performance Modeling for Inter/Intra-Die Variations,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 721-727, Nov. 2005.
    [52]G. Yu and P. Li, ¡§Efficient Look-Up-Table-Based Modeling for Robust Design of Sigma-Delta ADCs,¡¨ IEEE Trans. on Circuits and Systems I, Reg. Papers, vol. 54, no. 7, pp. 1513-1528, Jul. 2007.
    [53]S. R. Nassif, ¡§Modeling and Analysis of Manufacturing Variations,¡¨ in Proc. Conf. Custom Integrated Circuits, pp. 223-228, May 2001.
    [54]K. Kang, B. C. Paul, and K. Roy, ¡§Statistical Timing Analysis Using Levelized Covariance Propagation,¡¨ in Proc. Design, Automation and Test in Europe, pp. 764-769, Mar. 2005.
    [55]H. Chang and S. S. Sapatnekar, ¡§Statistical Timing Analysis Considering Spatial Correlations Using a Single PRET-Like Traversal,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 621-625, Nov. 2003.
    [56]C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, D. K. Beece, J. Piaget, N. Venkateswaran, and J. G. Hemmett, ¡§First-Order Incremental Block-Based Statistical Timing Analysis,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2170-2180, Oct. 2006.
    [57]K. Kang, B. C. Paul, and K. Roy, ¡§Statistical Timing Analysis Using Levelized Covariance Propagation Considering Systematic and Random Variations of Process Parameters,¡¨ ACM Trans. on Design Automation of Electronic Systems, vol. 11, no. 4, pp. 848-879, Oct. 2006.
    [58]J. Le, X. Li, and L. T. Pileggi, ¡§STAC: Statistical Timing Analysis with Correlation,¡¨ in Proc. Design Automation Conf., pp. 343-348, Jun. 2004.
    [59]X. Liang and D. Brooks, ¡§Microarchitecture Parameter Selection to Optimize System Performance Under Process Variation,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 429-436, Nov. 2006.
    [60]Y. Cao and L. T. Clark, ¡§Mapping Statistical Process Variations toward Circuit Performance Variability: An Analytical Modeling Approach,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1866-1873, Oct. 2007.
    [61]J. Zou, D. Mueller, H. E. Graeb, and U. Schlichtmann, ¡§A PLL Hierarchical Optimization Methodology Considering Jitter, Power and Locking time,¡¨ in Proc. Design Automation Conf., pp. 19-24, Jul. 2006.
    [62]X. Mao, H. Yang, and H. Wang, ¡§Behavioral Modeling and Simulation of Jitter and Phase Noise in Fractional-N PLL Frequency Synthesizer,¡¨ in Proc. Behavioral Modeling Simulation Conf., pp. 25-30, Oct. 2004.
    [63]X. Lai and J. Roychowdhury, ¡§TP-PPV: Piecewise Nonlinear, Time-Shifted Oscillator Macromodel Extraction for Fast, Accurate PLL Simulation,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 269-274, Nov. 2006.
    [64]X. Lai and J. Roychowdhury, ¡§Advanced Tools for Simulation and Design of Oscillators/PLLs,¡¨ in Proc. Asia South Pacific Design Automation Conf., pp. 442-449, Jan. 2007.
    [65]R. Batra, P. Li, L. T. Pileggi, and W.-J. Chiang, ¡§A Behavioral Level Approach for Nonlinear Dynamic Modeling of Voltage-Controlled Oscillators,¡¨ in Proc. Custom Integrated Circuits Conf., pp. 717-720, Sep. 2005.
    [66]C.-H. Lee, K. McClellan, and J. Choma, Jr, ¡§Supply Noise Insensitive PLL Design through PWL Behavioral Modeling and Simulation,¡¨ IEEE Trans. on Circuits and Systems II, Exp. Briefs, vol. 48, no. 12, pp. 1137-1144, Dec. 2001.
    [67]E. S. Fetzer, ¡§Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design,¡¨ IEEE Design & Test of Computers, vol. 23, pp. 476-483, Jun. 2006.
    [68]D. Ghai, S. P. Mohanty, and E. Kougianos, ¡§Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design,¡¨ in Proc. Int. Symp. Quality Electronic Design, pp. 330-333, Mar. 2008.
    [69]X. Ye, P. Li, and F. Liu, ¡§Practical Variation-Aware Interconnect Delay and Slew Analysis for Statistical Timing Verification,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 54-59, Nov. 2006.
    [70]V. Iyengar, J. Xiong, S. Venkatesan, V. Zolotov, D. Lackey, P. Habitz, and C. Visweswariah, ¡§Variation-Aware Performance Verification Using At-Speed Structural Test and Statistical Timing,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 405-412, Nov. 2007.
    [71]Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas, ¡§Impact of Interconnect Variations on the Clock Skew of a Gigahertz Microprocessor,¡¨ in Proc. Design Automation Conf., pp. 168-171, Jun. 2000.
    [72]L. Zhang, W. Chen, Y. Hu, J. A. Gubner, and C. C.-P. Chen, ¡§Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model,¡¨ in Proc. Design Automation Conf., pp. 83-88, Jun. 2005.
    [73]H. L. Abdel-Malek, A. S. O. Hassan, E. A. Soliman, and S. A. Dakroury, ¡§The Ellipsoidal Technique for Design Centering of Microwave Circuits Exploiting Space-Mapping Interpolating Surrogates,¡¨ IEEE Trans. on Microwave Theory and Techniques., vol. 54, no. 10, pp. 3731-3738, Oct. 2006.
    [74]G. Stehr, H. E. Graeb, and K. J. Antreich, ¡§Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier¡VMotzkin Elimination,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 10, pp. 1733-1748, Oct. 2007.
    [75]A. Agarwal and R. Vemuri, ¡§Hierarchical Performance Macromodels of Feasible Regions for Syndissertation of Analog and RF Circuits,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 430-436, Nov. 2005.
    [76]G. Gielen, T. McConaghy, and T. Eeckelaert, ¡§Performance Space Modeling for Hierarchical Syndissertation of Analog Integrated Circuits,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 881-886, Nov. 2005.
    [77]T. Eeckelaert, T. McConaghy, and G. Gielen, ¡§Efficient Multiobjective Syndissertation of Analog Circuits Using Hierarchical Pareto-Optimal Performance Hypersurfaces,¡¨ in Proc. Design, Automation and Test in Europe, pp. 1070-1075, Mar. 2005.
    [78]F. De Bernardinis and A. Sangiovanni-Vincentelli, ¡§A Methodology for System-Level Analog Design Space Exploration,¡¨ in Proc. Design, Automation and Test in Europe, pp. 676-677, Mar. 2004.
    [79]F. De Bernardinis, M. I. Jordan, and A. Sangiovanni-Vincentelli, ¡§Support Vector Machines for Analog Circuit Performance Representation,¡¨ in Proc. Design Automation Conf., pp. 964-969, Jun. 2003.
    [80]G. Stehr, H. E. Graeb, and K. Antreich, ¡§Feasibility Regions and Their Significance to the Hierarchical Optimization of Analog and Mixed-Signal systems,¡¨ in Proc. Int. Series of Numerical Math., pp. 167-184, Oct. 2003.
    [81]M. del Mar Hershenson, ¡§Design of Pipeline Analog-to-Digital Converters via Geometric Programming,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 317-324, Nov. 2002.
    [82]M. Vogels and G. Gielen, ¡§Architectural Selection of A/D Converters,¡¨ in Proc. Design Automation Conf., pp. 974-977, Jun. 2003.
    [83]O. Bajdechi, G. Gielen, and J. H. Huijsing, ¡§Systematic Design Exploration of Delta-Sigma ADCs,¡¨ IEEE Trans. on Circuits and Systems I, Reg. Papers, vol. 51, no. 1, pp. 86-95, Jan. 2004.
    [84]B. De Smedt and G. Gielen, ¡§WATSON: Design Space Boundary Exploration and Model Generation for Analog and RF IC Design,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 2, pp. 213-223, Feb. 2003.
    [85]G. Van der Plas, G. Debyser, F. Leyn, K. Lampaert, J. Vandenbussche, G. Gielen, W. Sansen, P. Veselinovic, and D. Leenaerts, ¡§AMGIE¡XA Syndissertation Environment for CMOS Analog Integrated Circuits,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1037-1058, Sep. 2001.
    [86]R. Phelps, M. Krasnicki, R. A. Rutenbar, L. R. Carley, and J. R. Hellums, ¡§Anaconda: Simulation-Based Syndissertation of Analog Circuits via Stochastic Pattern Search,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 6, pp. 703-717, Jun. 2000.
    [87]K. Antreich, H. E. Graeb, and C. Wieser, ¡§Circuit Analysis and Optimization Driven by Worst-Case Distances,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, no. 1, pp. 57-71, Jan. 1994.
    [88]R. Schwencker, F. Schenkel, H. E. Graeb, and K. Antreich, ¡§ The Generalized Boundary Curve¡Xa Common Method for Automatic Nominal Design and Design Centering of Analog Circuits,¡¨ in Proc. Design, Automation and Test in Europe, pp. 42-47, Mar. 2000.
    [89]D. M. Colleran, C. Portmann, A. Hassibi, C. Crusius, S. S. Mohan, S. Boyd, T. H. Lee, and M. del Mar Hershenson, ¡§Optimization of Phase-Locked Loop Circuits via Geometric Programming,¡¨ in Proc. Custom Integrated Circuits Conf., pp. 377-380, Sep. 2003.
    [90]X. Li, Y. Zhan, and L. T. Pileggi, ¡§Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits,¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 831-843, May 2008.
    [91]X. Li, P. Gopalakrishnan, Y. Xu, and L. T. Pileggi, ¡§Robust Analog/RF Circuit Design with Projection-Based Performance Modeling¡¨ IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 1, pp. 2-15, Jan. 2007.
    [92]C.-C. Kuo, M.-J. Lee, C.-N. J. Liu, and C.-J. Huang, ¡§Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models,¡¨ IEEE Trans. on Circuits and Systems I, Reg. Papers, vol. 56, no. 6, pp. 1160-1172, Jun. 2009.
    [93]F. Schenkel, M. Pronath, S. Zizala, R. Schwencker, H. E. Graeb, and K. Antreich, ¡§Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search,¡¨ in Proc. Design Automation Conf., pp. 858-863, Jun. 2001.
    [94]H. E. Graeb, S. Zizala, J. Eckmueller, and K. Antreich, ¡§The Sizing Rules Method for Analog Integrated Circuit Design,¡¨ in Proc. Int. Conf. Computer-Aided Design, pp. 343-349, Nov. 2001.
    [95]H. E. Graeb, Analog Design Centering and Sizing, Springer, 2007.
    [96]I. Jolliffe, Principal Component Analysis, Wiley, 2005.
    Advisor
  • Chien-Nan Liu(¼B«Ø¨k)
  • Files
  • 945401022.pdf
  • approve immediately
    Date of Submission 2009-07-15

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have dissertation-related questions, please contact with the NCU library extension service section.
    Our service phone is (03)422-7151 Ext. 57407,E-mail is also welcomed.