Title page for 93521053


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Student Number 93521053
Author Wei-Ting Yen(ÃCÞ³§Ê)
Author's Email Address No Public.
Statistics This thesis had been viewed 2247 times. Download 1691 times.
Department Electrical Engineering
Year 2005
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title A Self-Aligned Nanowire MOSFET
Date of Defense 2006-07-05
Page Count 43
Keyword
  • Self-aligned
  • Silicon nanowires
  • Abstract In this thesis, the formation of NiSi silicide using rapid thermal annealing is investigated. The NiSi salicidation process is, then, incorporated into the fabrication of novel self-aligned nanowire MOSFET devices structure. A self-aligned nanowire MOSFET fabricated on a 70-nm-thick SOI wafer, features advanced process modules including recessed nitride spacer, fully silicided (NiSi) source/drain, and self-aligned poly silicon gate. In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D. Since LOCOS process is integrated in a nanowire MOSFET process flow, one doesn¡¦t require e-beam lithography to do precise alignment for ultra narrow gate stacked structure. A self-aligned poly gate technology is utilized to improve manufacturing yield efficiently. A recessed spacer structure is carried out using hot phosphoric acid etching, which is highly selective between Si3N4 and Si. Edge effects of Ni polycide formation are enhanced by such recessed spacer and result in Rs reduction further. Finally, the device performance is evaluated.
    Table of Content Contents
    Chapter 1. Introduction....................................................................................................... 1
    1-1. History.............................................................................................................. 1
    1-2. SOI-MOSFET.................................................................................................. 2
    1-3. Experimental motivation and objective........................................................... 5
    Chapter 2. Silicidation......................................................................................................... 7
    2-1. History.............................................................................................................. 7
    2-2. Salicidation development................................................................................. 7
    2-3. NiSi film properties......................................................................................... 9
    2-4. NiSi process....................................................................................................10
    2-5. NiSi sheet resistance...................................................................................... 12
    2-6. Back-end process............................................................................................14
    2-7. Application.....................................................................................................15
    Chapter 3. Nanowire MOSFET Fabrication Process........................................................ 18
    3-1. Device structure........................................................................................... 18
    3-2. Main process flow........................................................................................ 19
    3-3. Devices fabrication process......................................................................... 20
    Chapter 4. Experimental results and discussion................................................................ 28
    4-1. Short channel effects.................................................................................... 28
    4-2. Device operation mode................................................................................ 30
    4-3. Reduced driving current.............................................................................. 32
    4-4. Temperature dependence..............................................................................36
    Chapter 5. Conclusion....................................................................................................... 40
    References......................................................................................................................... 41
    Reference [1] S. E. Thompson et al., ¡§A 90-nm logic technology featuring strained-silicon,¡¨ IEEE Trans. Electron Devices, vol. 51, p. 1790. 2004.
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    [4] D. Connelly et al., ¡§Ultra-Thin-Body Fully Depleted SOI Metal Source/Drain n-MOSFETs and ITRS Low-Standby-Power Targets through 2018,¡¨ IEDM Technical Digest, 2005.
    [5] H. Park et al., ¡§High performance CMOS devices on SO1 for 90 nm technology enhanced by RSD (raised source/drain) and thermal cycle/spacer engineering,¡¨ IEDM Technical Digest, p. 635. 2003.
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    [14] T. Ghani et al., ¡§A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,¡¨ IEDM Technical Digest, p. 978. 2003
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    [18] H. Wang et. al., ¡§The behavior of narrow-width SOI MOSFET¡¦s with mesa isolation ,¡¨ IEEE Trans. Electron Devices, vol. 47, p.593. 2000.
    [19] D. A. Neamen, Semiconductor Physics and Devices, McGraw-Hill, 2002
    [20] S. H. Zaidi et. al., ¡§Multiple nanowire gate field effect transistors,¡¨ IEEE Nano Devices, p. 189. 2001.
    [21] J. D. Plummer et al., Silicon VLSI Technology, Prentice-Hall, Inc., 2000
    [22] C. Sorin et. al., ¡§Introduction to silicon on insulator materials and devices,¡¨ Microelectronic Engineering, vol.39, p.145.1997.
    [23] H. Fritz et. al., ¡§Very small MOSFET¡¦s for low-temperature operation,¡¨ IEEE Trans. Electron Devices, vol. 24, p. 218. 1977.
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    [25] N. Lindert et. al., ¡§Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,¡¨ IEEE Electron Device Lett., vol. 22, p. 487. 2001.
    Advisor
  • Pei-Wen Li(§õ¨Ø¶²)
  • Files
  • 93521053.pdf
  • approve immediately
    Date of Submission 2006-07-12

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