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Student Number 93521039
Author Chun-Hsien Wu(dT)
Author's Email Address No Public.
Statistics This thesis had been viewed 722 times. Download 235 times.
Department Electrical Engineering
Year 2009
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Efficient Diagnostic Data Compression and DFT Schemes for Embedded Memory Applications
Date of Defense 2010-07-20
Page Count 97
Keyword
  • BISD
  • BIST
  • embedded memory
  • viterbi
  • Abstract With the rapid development of electronic technology, the applications of embedded memories and relative testing techniques have become one of the most important subjects. For general embedded memories and their applications, this thesis presents two associated techniques of memory test/diagnosis. In the first part, a high-efficiency diagnostic data compression scheme is proposed. To the characteristic of March test algorithms, the proposed compression scheme can eliminate large amount of redundant fault syndromes. At the same time, the built-in self repair circuitry will be reused to reduce the area cost of the BISD design. The experimental results show that the compression scheme can reach 93% diagnostic data reduction ratio for mixed fault distributions; and 75% data reduction ratio is made for merely single cell faults with the simulation setting. It reveals that the proposed diagnostic data compression scheme exhibits excellent compression ability for all kinds of fault distributions. In the second part, a BISTed Viterbi decoder design is presented. A Viterbi decoder is a widely-used module in the field of wireless communication. To ensure the decoding ability of the decoder, it is an issue for IC designers to ascertain the correctness of the chips. In the proposed DFT scheme, the characteristic of a Viterbi decoder is used to facilitate the test procedures. With the intrinsic feedback path, the process of pattern deriving and delivering for a typical Viterbi decoder can be performed. The DFT scheme makes the patterns go through the logic circuit, and then to the subsequent embedded memory, enhancing the test integrity of a Viterbi decoder. In the way, both the testing for logic and that for memory components can proceed simultaneously; on another hand, the embedded BIST module can cover more time-associated faults; it will advance the quality and reliability of the Viterbi decoder design. The proposed DFT scheme can reach 93.6% fault coverage for stuck-at faults of the logic circuit in a typical Viterbi decoder, and the area overhead is around 8.2%
    Table of Content Chapter 1 Introduction KKKKKKKKKKKKKKKKKKK...1
    Chapter 2 Data Compression Techniques for Embedded Memories K..6
    2.1.Preliminary KKKKKKKKKKKKKKKKKKK....6
    2.2.The Compression Scheme of Diagnostic Data KKKKKK.9
    2.2.1.Hamming Syndrome Elimination KKKKKKKKKKK10
    2.2.2.Fault Address Elimination KKKKKKKKKKKKKK14
    2.3.Architecture of the Built-In Self-Diagnosis Circuit KKKK28
    2.4.Data Exportation Mechanism KKKKKKKKKKKK..32
    2.5.Codeword Format KKKKKKKKKKKKKKKKK.36
    2.6.Analysis for Area vs. Compression Efficiency KKKKKK42
    2.7.Experimental Results KKKKKKKKKKKKKKKK46
    Chapter 3 Built-In Self-Test Scheme for Viterbi Decoder KKKKKK52
    3.1Preliminary KKKKKKKKKKKKKKKKKKKK52
    3.1.1.Viterbi Algorithm and Trellis Diagram KKKKKKKK..54
    3.1.2.Viterbi Decoder KKKKKKKKKKKKKKKKKK.57
    3.2.Testability Analysis for ACS Unit KKKKKKKKKKK59
    3.3.Proposed Test Strategy with PM Feedback KKKKKKK69
    3.4.Experimental Results KKKKKKKKKKKKKKKK77
    Chapter 4 Conclusions and Future Works KKKKKKKKKKKK83
    Reference KKKKKKKKKKKKKKKKKKKKKKKKKK..85
    Reference [1] Po-Kai Chen, Yu-Tsao Hsing, and Cheng-Wen Wu, On Feasibility of HOY-A Wireless Test Methodology for VLSI Chips and Wafers, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2006, pp.1-4
    [2]Cheng-Wen Wu, Chih-Tsun Huang, Shi-Yu Huang, Po-Chiun Huang, Tsin-Yuan Chang, and Yu-Tsao Hsing, The HOY Tester - Can IC Testing Go Wireless?, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), April 2006, pp.1-4
    [3] Te-Wen Ko, Yu-Tsao Hsing, Cheng-Wen Wu, and Chih-Tsun Huang, Stable Performance MAC Protocol for HOY Wireless Tester under Large Population, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 25-27 April 2007, pp.1-4
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    [7]Jin-Fu Li and Cheng-Wen Wu, "Memory Fault Diagnosis by Syndrome Compression", in Proc. Design, Automation and Test in Europe (DATE), 13-16 Mar. 2001, pp. 97-101
    [8]Jin-Fu Li, Ruey-Shing Tzeng and Cheng-Wen Wu, "Using Syndrome Compression for Memory Built-In Self-Diagnosis", in Proc. International Symposium on VLSI technology, Systems, and Applications, 18-20 Apr. 2001, pp 303 - 306
    [9]Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Shen-Tien Lin and Wen-Ching Wu, "Embedded Memory Diagnostic Data Compression Using Differential Address", IEEE International Symposium on VLSI Design, Automation and Test (VLSI-TSA-DAT), 27-29 Apr. 2005, pp. 20-23
    [10]Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang and Wen-Ching Wu, "A Memory Built-In Self-Diagnosis Design with Syndrome Compression", in Proc. IEEE International Workshop on Current and Defect Based Testing (DBT), 25 Apr. 2004, pp. 99-104
    [11]Chen, J.T., Khare, J., Walker, K., Shaikh, S., Rajski, J. and Maly W., "Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring", in Proc. International Test Conference, 30 Oct.-1 Nov. 2001, pp. 258-267
    [12]C.-F Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W.Wu, Error Catch and Analysis for Semiconductor Memories Using March Tests, in Proc. IEEE Int. Conf. Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468-471
    [13]C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, Built-In RedundancyAnalysis for Memory Yield Improvement, IEEE Trans. Reliab., vol. 52, no. 4, pp. 386-399, Dec. 2003.
    [14]T.-W. Tseng, J.-F. Li, and C.-C. Hsu, ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs, IEEE Trans. on VLSI Systems, vol. 18, issue 6, pp. 921-932, Jun. 2010
    [15]A. J. Viterbi, Error Bounds for Convolutional Codes and an Asymptotically OptimumDecoding Algorithm, IEEE Trans. Inform. Theory, vol. IT-13, pp. 260V269, Apr. 1967
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    [17] P. J. Black and T. H. Meng, A 140-Mb/s 32-State Radix-4 Viterbi Decoder, IEEE J.Solid-State Circuits, vol. 27, pp. 1877V1885, Dec. 1992
    [18]C. B. Shung, H-D. Lin, R. Cypher, P. H. Siege1 and H. K. Thapar, Area-Efficient Architecture for the Viterbi Algorithm Part 11: Applications, IEEE Trans. on Commun., vol. 41, pp. 802-807, May 1993
    [19]M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, High-Performance LSI Architecture for the Viterbi Algorithm, IEEE Trans. on Commun., vol. 45, pp. 168-176,Feb. 1997
    [20]Gennady Feygin and P.G. Gulak. .Architectural Tradeoff for Survivor Sequence Memoryin Viterbi Decoder.. IEEE Trans. on Commun., vol.. 41, pp. 425-429, 1998
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    Advisor
  • Jin-Fu Li(i)
  • Files
  • 93521039.pdf
  • approve immediately
    Date of Submission 2010-08-10

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