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Student Number 93521020
Author YU-JEN HUANG(¶À·ì¯u)
Author's Email Address 93521020@cc.ncu.edu.tw
Statistics This thesis had been viewed 804 times. Download 5 times.
Department Electrical Engineering
Year 2011
Semester 2
Degree Ph.D.
Type of Document Doctoral Dissertation
Language English
Title Efficient Test and Yield-Enhancement Techniques for Multi-Core/Die System Chips
Date of Defense 2012-04-18
Page Count 209
Keyword
  • 3D IC
  • built-in self-repair
  • built-in self-test
  • diagnosis
  • memory testing
  • multi-core
  • random access memory (RAM)
  • System-on-Chip (SOC)
  • through-silicon-via (TSV)
  • yield-enhancement
  • Abstract Three-dimensional (3D) technology vertically integrating multiple 2D dies using the through-silicon-via (TSV) is one emerging integrated circuit design technology. It offers many advantages over the 2D integration technology. However, many challenges, such as the design, manufacturing, test, yield, and etc., should be overcome before the volume production of 3D ICs become possible. Among these challenges, test and yield are two key challenges. Effective test and yield-enhancement techniques are thus important for 3D ICs.
    A 3D IC consists of multiple dies in which a die may be designed with multi-core architecture. Regardless of the multi-core die or the multi-die chip, memories usually dominate a large portion of the silicon area. In the first part of the thesis, therefore, we focus on the testing of RAMs in multi-core dies. Two low-area test schemes are proposed to test small RAMs, an enhanced IEEE 1500 wrapper-based test scheme and a scalable and low-cost built-in-self test (BIST) scheme. The enhanced IEEE 1500 wrapper-based test scheme utilizes existing IEEE standard 1500 wrappers to test RAMs connected to the IEEE 1500 wrappers. Experimental results show that the additional area cost for extending the IEEE 1500 wrapper to an enhanced one is small, which is only about 0.58% for a 64K-bit single-port RAM and only 0.57% for a 64K-bit two-port RAM in 90nm technology. The scalable and low-cost BIST scheme for an array of memories can reduce the area cost without incurring long testing time and increase the scalability. Furthermore, a fault-location approach is proposed to identify the positions of faulty bits in a faulty word. Simulation results show that the proposed BIST scheme has small area cost, e.g., the BIST circuit for 16 1024¡Ñ64-bit RAMs only needs about 0.89%hardware overhead. A test chip is also implemented to demonstrate the proposed BIST scheme for 9 RAMs.
    Clearly, the test and yield of TSV are very important for 3D ICs. To detect and tolerate defective TSVs, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3D ICs in the second part of the thesis. The BISR scheme, arranging the TSVs into arrays similar to memories, can provide high repair yield. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.
    In the third part of the thesis, we discuss more complex fault models of TSVs ¡X the crosstalk faults. Test algorithms for testing different types of crosstalk faults of TSVs are proposed. Then, a BIST architecture and the wrapper-based test architecture are proposed to realize the test algorithms for TSVs. Simulation results show that the area overhead of the proposed BIST circuit for a 32¡Ñ16 TSV array with 9T crosstalk faults is 28.1% using 0.18£gm CMOS technology, where each TSV cell size is 15 ¡Ñ 15£gm2. However, the area overhead of the BIST circuit is only 1.86% to a 25mm2 die. The area overhead of the proposed wrapper-based test architecture is 60.6% for the same TSV array which can save 15% area overhead compared with the typical two-storage wrapper test architecture which has 73.92% area overhead to the TSV array.
    In the application point of view, multi-core die stacked with memories has been considered as one good candidate for 3D ICs. As aforementioned, the yield is one critical issue for 3D ICs, therefore, we propose yield-enhancement techniques, one-level and two-level reconfiguration scheme, for homogeneous multi-core memory and processor stacked 3D ICs. For a memory and processor stacked 3D ICs, a horizontal shifting reconfiguration scheme is added in the memory die while a vertical shifting reconfiguration scheme is added in the processor die. Then memory and processor cores can be swapped which can make as many good memory-processor pairs as possible. Also, heuristic reconfiguration algorithms are developed to fast calculate the reconfigurability of the memory and processor dies. Then the yield of 3D multi-core ICs can be improved by the proposed yield enhancement techniques. Experimental results show that the proposed reconfiguration schemes can significantly increase the yield from 1% to 11% using negligible area overhead. For example, if the 3D IC is a 63-out-of-64 system, the proposed one-level and two-level reconfigurations schemes can increase 1.71% and 6.08% of final yield compared with randomly wafer-to-wafer stacking without any yield-enhancement technique.
    Table of Content 1 Introduction 1
    1.1 3D Integration Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
    1.1.1 TSV Techniques and Bonding Techniques . . . . . . . . . . . . . . . . . . 1
    1.1.2 3D IC Architectures and Applications . . . . . . . . . . . . . . . . . . . . 3
    1.1.3 Challenges of 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
    1.2 Test and Yield-Enhancement Techniques for 2D Dies . . . . . . . . . . . . . . . . 6
    1.2.1 2D System-on-Chips (SOCs) in a 3D IC . . . . . . . . . . . . . . . . . . . 6
    1.2.2 Memory Built-In Self-Test Circuit . . . . . . . . . . . . . . . . . . . . . . 8
    1.2.3 IEEE Standard 1500 Architecture . . . . . . . . . . . . . . . . . . . . . . 9
    1.2.4 Existing Memory Built-In Self-Test Schemes . . . . . . . . . . . . . . . . 10
    1.3 Test and Yield-Enhancement Techniques for 3D Dies . . . . . . . . . . . . . . . . 13
    1.3.1 Defects in TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
    1.3.2 Testing of 3D ICs and TSVs . . . . . . . . . . . . . . . . . . . . . . . . . 14
    1.3.3 Existing TSV Redundancy and Reconfiguration Schemes . . . . . . . . . . 16
    1.4 Thesis Scope and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
    1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
    2 Built-In Self-Test Techniques for Small RAMs in SOCs 22
    2.1 Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . 23
    2.1.1 Architecture of the Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . 23
    2.1.2 Operations of the Proposed Enhanced 1500 Wrapper . . . . . . . . . . . . 25
    2.1.3 Implementation of Wrapper Cell and Address Generator . . . . . . . . . . 27
    2.1.4 Multi-Port RAM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
    2.1.5 Test Time Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . . 31
    2.2 Pipelined BIST Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
    2.2.1 BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
    2.2.2 BIST Sharability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
    2.2.3 Test Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
    2.2.4 BIST for an Array of Memories . . . . . . . . . . . . . . . . . . . . . . . 42
    2.2.5 Support of Interconnection Test . . . . . . . . . . . . . . . . . . . . . . . 43
    2.3 Memory Repair and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
    2.3.1 Memory Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
    2.3.2 Memory Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
    2.3.3 BIST Modification for Memory Diagnosis . . . . . . . . . . . . . . . . . . 49
    2.4 Simulation and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . 51
    2.4.1 Design of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 51
    2.4.2 Analysis of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 53
    2.4.3 Design of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . . 59
    2.4.4 Analysis of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . 63
    2.4.5 Architecture of the Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . 66
    2.4.6 Results of Wafer-level Test . . . . . . . . . . . . . . . . . . . . . . . . . . 66
    2.4.7 Results of Post-bond Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
    2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
    3 Self-Test and Repair for TSVs in 3D ICs 73
    3.1 Proposed Testing Scheme for TSV Arrays . . . . . . . . . . . . . . . . . . . . . . 74
    3.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
    3.1.2 Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
    3.1.3 KGS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
    3.2 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
    3.2.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 81
    3.2.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
    3.2.3 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
    3.3 Proposed TSV Redundancy and Reconfiguration Scheme . . . . . . . . . . . . . . 87
    3.4 Proposed BISR Scheme for TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 92
    3.4.1 Overview of the BISR scheme . . . . . . . . . . . . . . . . . . . . . . . . 92
    3.4.2 BISR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
    3.4.3 BISR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
    3.5 Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
    3.5.1 Connection of Repair Register and Fuse . . . . . . . . . . . . . . . . . . . 99
    3.5.2 Design of Fuse Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103
    3.6 Analysis and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . 104
    3.6.1 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
    3.6.2 Fuse Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
    3.6.3 Yield Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
    3.6.4 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
    3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
    4 Testing Crosstalk Faults of TSVs in 3D ICs 116
    4.1 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
    4.1.1 5-TSV and 9-TSV Fault Models . . . . . . . . . . . . . . . . . . . . . . . 118
    4.1.2 Coupling Effects of TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 119
    4.2 Proposed Test Algorithms for Crosstalk Faults of TSVs . . . . . . . . . . . . . . . 121
    4.2.1 Parallel Test Algorithms and Wrapper-based Test Scheme . . . . . . . . . 121
    4.2.2 Test Algorithms for 5T-XF using BIST Scheme . . . . . . . . . . . . . . . 125
    4.2.3 Test Algorithms for 9T-XF using BIST Scheme . . . . . . . . . . . . . . . 126
    4.3 Proposed Testing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
    4.3.1 Proposed BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 129
    4.3.2 Test Operation Flow of the BIST Scheme . . . . . . . . . . . . . . . . . . 132
    4.4 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
    4.4.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 133
    4.4.2 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
    4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
    5 Yield-Enhancement Techniques for Memory and Processor Stacked 3D ICs 141
    5.1 Yield of Multi-Core 2D and 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . 142
    5.2 Yield-Enhancement Techniques for 3D ICs . . . . . . . . . . . . . . . . . . . . . 143
    5.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
    5.4 Proposed Yield Enhancement Techniques . . . . . . . . . . . . . . . . . . . . . . 145
    5.4.1 Proposed Yield-Enhancement Flow . . . . . . . . . . . . . . . . . . . . . 145
    5.4.2 Proposed One-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 146
    5.4.3 Proposed Two-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 153
    5.4.4 Wafer Matching Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
    5.5 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
    5.5.1 Area Overhead and Yield Model . . . . . . . . . . . . . . . . . . . . . . . 159
    5.5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
    5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
    6 Conclusion and Future Work 169
    6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
    6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
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