Title page for 92521026


[Back to Results | New Search]

Student Number 92521026
Author shin-Syong Guo(@)
Author's Email Address 92520126@cc.ncu.edu.tw
Statistics This thesis had been viewed 2630 times. Download 1560 times.
Department Electrical Engineering
Year 2004
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Design of CMOS Transmitter Circuit for 2.5Gbps NRZ Data Transmission
Date of Defense 2005-07-08
Page Count 65
Keyword
  • serial
  • tramsmitter
  • Abstract Design of CMOS Transmitter Circuit for 2.5Gps NRZ Data Transmission
    Abstract
    Under the development of the network and computer operated speed in recent years, a trend of data transmission and studying at high-speed serial communication is growing. It is pointed out that the high-speed serial link interface is replacing gradually the conventional parallel bus interface in large data transmission by the development of PCI bus from PCI 1.0 to PCI-Express. The serial link technique is used at the optical communication in the past. However, it replaces the high-speed parallel data bus. The serial link technique is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end.
    This thesis focuses on the application of wire communication or serial link data transmission interface and takes the specification of PCI-Express as the objective in implementation. This work uses the multi-phase clock to generate the serial signal. In the output driver end, there is a large influence on the signal integrity due to the transmission line effect. So, this work achieves the well impedance match by adjusting the load. This thesis implements the transmitter chip fabricated in a TSMC 0.18gm CMOS technology. The transmitter operates at 2.5Gbps with 1.8V supply and the chip area is 685gm685gm. The whole chip power consumption is 91.24mW.
    Table of Content Contents
    Chapter 1 Introductions1
    1.1 Era of Data Transmission1
    1.2 Thesis Organization2
    Chapter 2 Fundamental of Serial Links3
    2.1 Parallel Links and Point-to-Point Links3
    2.1.1 BUS Links3
    2.1.2 Point-to-Point Links7
    2.1.3 Serial Links versus Parallel9
    2.2 The Concept of Signal Integrity12
    2.2.1 Transmission Line13
    2.2.2 Reflection16
    2.2.3 Termination19
    2.3 Output Driver21
    2.3.1 Push-Pull Voltage-Mode Driver22
    2.3.2 Pull-Down Current-Mode Driver23
    2.3.3 Differential Current-Mode Driver24
    Chapter 3 Transmitter System Architecture26
    3.1 Architecture of Serial Links Transceiver26
    3.1.1 Transmitter Architecture28
    3.2 PRBS Generation and Data Synchronization30
    3.2.1 PRBS generation30
    3.2.2 Data Synchronization31
    3.3 Serializer33
    3.4 Current-mode Driver and On-Chip termination37
    3.4.1 CML Output Structure37
    3.4.2 AC-coupling CML circuit39
    3.4.3 On-Chip Termination Circuit41
    3.5 Multi-Phase Clock Generator Architecture46
    3.6 Simulation Result47
    3.6.1 Transmitter48
    3.6.2 On-Chip Termination51
    3.6.3 Multi-Phase Clock Generator54
    3.6.4 Transmitter Chip Measurement Result56
    Chapter 4 Conclusion & Future Work60
    4.1 Conclusion60
    4.2 Future Work61
    Reference  63
    Reference Reference
    [1] H.Johnson, M. Graham, "High-Speed Digitial Design --- A Handbook of Black Magic," Prentice-Hall, Inc. 1993.
    [2] Tom Granberg, "Handbook of Digital Techniques For High-Speed Design" Prentice-Hall, Inc. 2004.
    [3] Hong-Gee Huang, "Transmission Line Termination Methodology for Digital Signal Transmission," NCU Thesis. 1999.
    [4] Shao-Ming Chang, "A 2.5V, 0.35um, 2.5Gbps transceiver design," NCU Tesis. 2001.
    [5] K. J. Wong, H. Hatamkani, M. Mansuri, C. K. Yang, "A 27-mW 3.6-Gb/s I/O Transceiver," IEEE Journal of Solid-State Crcuits, 2004
    [6] B. Razavil, "Design of Integrated Circuits for Optical Communications," McGraw-Hill, 2003
    [7] Chang, K.-Y.K.; Wei, J.; Li, S.; Li, Y.; Donnelly, K.; Huang, C.; Sidiropoulos, S. "A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs" Symposium on VLSI Circuits Digest of Technical Papers, 2002.
    [8] Chih-Kong Ken Yang; Ramin Farjad-Rad; Horowitz, M.A. "A 0.5-gm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling" IEEE Journal of Solid-State Circuits, 1998.
    [10] PCISIG GROUP, "PCI-ExpressTM Base Specification Revision 1.0a"
    [11] Farjad-Rad, R.; Yang, C.-K.K.; Horowitz, M.A. "A 0.3-gm CMOS 8-Gb/s 4-PAM serial link transceiver," IEEE Journal of Solid-State Circuits, 2000.
    [12] Lee, M.-J.E.; Dally, W.J.; Chiang, P. "Low-power area-efficient high-speed I/O circuit techniques," IEEE Journal of Solid-State Circuits, 2000.
    [13] K. Koo, J. Seo, J. Kim, "Digitally tuneable on-chip resistor in CMOS for high-speed data transmission," 2003. ISCAS '03 Proceedings of the 2003 International Symposium on Circuits and Systems, 2003.
    [14] H.B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI," Addison-Wesley Publication Company, 1990.
    [15] K. Donnelly, "A 660 MB/s interface megacell portable circuit in 0.3gm-0.7gm CMOS ASIC," 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.290-291, Feb. 1996.
    [16] M. Galles, et al., "Spider: a high-speed network interconnect," IEEE Micro, vol.17, no.1, pp. 34-39, Jan.-Feb. 1997.
    [17] N. Kushiyama, et al., "A 500-megabyte/s data-rate 4.5M DRAM," IEEE Journal of Solid-State Circuits, vol.28, no.4, pp. 490-498, Apr. 1993.
    [18] E. Reese, et al., "A Phase-tolerant 3.8GB/s data-communication router for a multi-processor supercomputer backplane," 1994 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp.296-297, Feb. 1994.
    [19] A. Mu, et al., "A 285 MHz 6-port Plesiochronous Router Chip with Non-Blocking Cross-Bar Switch" Proceedings of 1996 IEEE Symposium on VLSI Circuits, pp.136-137, Jun. 1996.
    [20] J. Kusin, et al., "The Stanford FLASH Multiprocessor," Proceedings of the 21st International Symposium on Computer Architecture, ISCA-94, pp. 274-284.
    [21] N. McKeown, "Tina Tera: A Packer Switch Core," IEEE Micro, vol.17, no.1, pp.26-33, Jan.-Feb. 1997.
    [22] F. Tobagi, "Fast Packet Switch Architectures for Broad" Proceedings of the IEEE,vol.78, no.1, pp.133-167, Jan. 1990.
    [23] K.H. Cheng, et al., "A Dual-slope Phase Frequency Detector and Charge Pump Architecture to Achieve Fast Locking of Phase-Locked Loop," IEEE Trans. on Circuits and Systems Part II, Analog and Digital Signal Processing. Vol.50, pp. 892-896. Nov. 2003.
    [24] K.H. Cheng, et al., "A Low-power High-driving Ability Voltage Control Oscillator Used in PLL," International Journal of Electronics, vol. 91, no. 6, pp. 361-375, June 2004.
    [25] K.H. Cheng, et al., "A Fast-Lock DLL with Power-On Reset Circuit," IEICE Trans. on Fundamentals, Vol.E87-A No.9, pp.2210-2220, Sep. 2004.
    [26] R. Mooney, et al., "A 900Mb/s bidirectional signaling scheme," IEEE Journal of Solid-State Circuits, vol.30, no.12, pp.1538-1543, Dec. 1995.
    [27] T. Takahashi, et al., "A CMOS Gate Array with 600Mb/s Simutaneous Bidirectional I/O Circuits," IEEE Journal of Solid-State Circuits, vol.30, no.12, pp.1544-1546, Dec 1995.
    Advisor
  • Kuo-Hsing Cheng(G꿳)
  • Files
  • 92521026.pdf
  • approve immediately
    Date of Submission 2005-07-20

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have dissertation-related questions, please contact with the NCU library extension service section.
    Our service phone is (03)422-7151 Ext. 57407,E-mail is also welcomed.