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Student Number 92521022
Author Chia-Wei Su(ĬŰ)
Author's Email Address 92521022@cc.ncu.edu.tw
Statistics This thesis had been viewed 1957 times. Download 1258 times.
Department Electrical Engineering
Year 2008
Semester 1
Degree Ph.D.
Type of Document Doctoral Dissertation
Language English
Title Design and Implementation of Duty Cycle Adjustment and Clock Synchronization Circuits
Date of Defense 2008-10-27
Page Count 140
Keyword
  • clock synchronous circuit
  • duty cycle adjustment
  • Abstract With the increasing operating frequency in SoC, the clock skew would serious cause the incorrect system operation. Therefore, many synchronous circuits use to align clock skew, for example phase-locked loop (PLL), delay-locked loop (DLL), and synchronous mirror delay circuits (SMD) and etc. However, except the clock skew problem, clock duty cycle also needs to be accurate controlled to improve the reliability and correctness of circuits. In the double sampling system, the exact 50% clock duty cycle becomes quite important, for example double-sample rate SDRAM or double-sample rate ADC. Therefore, many clock duty cycle alignment circuits use in SoC, for example duty cycle corrector (DCC) and pulse width control loop (PWCL).
    First, this dissertation proposed a high linearity, fast-locking pulse width control loop with digitally programmable duty cycle correction for wide range operation. This circuit uses error amplifier to detect and achieve fast locking within 650ns. Using frequency detector to control multi-stage control stages, the proposed PWCL can stable operated within a wide-range of both input and output duty cycles over a wide frequency range. It can be operated with a frequency range from 1MHz to 1.3GHz and the duty cycle range of the input signal is from 30% to 70%. To extend the circuit application in SoC system, the proposed PWCL can use digital program to control output duty cycle, which the output duty cycle range is from 30% to 70% in step of 5%. This experimental chip has been fabricated using 0.18 gm CMOS process.
    Next, we developed a wide-range synchronous mirror delay with arbitrary input duty cycle for some clock synchronous circuits which need fast locking in SoC. The proposed wide-range SMD uses frequency detector to control multi-band delay monitor circuit to extend the operation frequency range which is from 200MHz to 1GHz. Using frequency selection scheme, the maximum locking cycle can be reduced to eight clock cycles. The fine tune circuit uses to calibrate the delay mismatch of each circuit and the maximum phase error is 6.7ps. The DFF-based MCC uses to correct operation in arbitrary input duty cycle and its duty cycle range at 200MHz is from 10% to 90%. To reduce power consumption, the proposed circuit would disable the non-operation circuit to achieve power saving and the maximum saving power is up to 40%.
    Finally, this dissertation aims at both demands of phase synchronization and duty cycle alignment to propose a wide-range digital synchronous buffer (DSCB) with digitally programmable output duty cycle. The digital synchronized delay circuit with SMD solves the long tracking time problem of PLL and DLL. The output duty cycle can be corrected and programmed by the high linearity PWCL. Using frequency detector, the multi-band delay lines are used to reduce the chip area, widen the operation frequency and save power consumption. The input buffer of the proposed SMD uses one-shot circuit to achieve the proposed wide-range digital synchronous buffer to accept wide input duty cycle range from 10% to 90%. The proposed synchronous buffer with programmable duty cycle has been fabricated using 0.18gm CMOS 1.8V process. The measurement results show that the operation frequency range is form 160MHz to 800MHz, the input duty cycle range is from 5% to 97%, and the preset output duty cycle range is form 35% to 70% in steps of 5%. The locking time is less than 250ns when phase and duty cycle are both locked. The phase error is less than 21ps and the duty cycle error is less than 1%. The power consumption is 12.8mW in 600MHz with save power mode that is less than normal mode about 35.9%. The core area is about 0.067mm2.
    In the dissertation, we proposed three clocking alignment circuits to let the application in SoC clock distribution network have more flexible and robust and use in different demand.
    Table of Content KnI
    AbstractIII
    xVII
    ContentsVIII
    Figure CaptionsXIII
    Table CaptionsXX
    Chapter 1Introduction1
    1.1.Demand for Clocking System1
    1.2.Overview of the Dissertation5
    Chapter 2Fundamentals of Duty Cycle Adjustment and Clock Synchronization Circuits7
    2.1.Duty Cycle Alignment Circuits7
    2.1.1.Open Loop Architecture8
    2.1.2.Close Loop Architecture9
    2.2.Clock Synchronization Circuits11
    2.2.1.Close-Loop Architecture12
    2.2.2.Open-Loop Architecture16
    Chapter 3Highly Linear and Fast Locking Pulse Width Control Loop19
    3.1.Architecture of Conventional Pulse Width Control Loops19
    3.1.1.Original Pulse Width Control Loop19
    3.1.2.Low-Voltage Pulse Width Control Loop20
    3.1.3.Fast-Locking Pulse Width Control Loop21
    3.1.4.Mutual-Correlated Pulse Width Control Loop21
    3.1.5.Signle-Path Pulse Width Control Loop22
    3.2.High-Linearity Pulse Width Control Loop23
    3.2.1.Multi-Stage Control Stage26
    3.2.2.Frequency Detector (FD)27
    3.2.3.Duty Cycle Detector (DCD)29
    3.2.4.Digital Controlled Charge Pump (DCCP)31
    3.3.Simulation and Comparison Results33
    3.3.1.Conventional CS versus Proposed CS33
    3.3.2.Differential Output Phase Error35
    3.3.3.Fast-Locking Simulation36
    3.3.4.Different Output Duty Cycle37
    3.3.5.Wide-Range Operation38
    3.3.6.Monte Carlo Analysis39
    3.4.Proposed PWCL Design42
    3.4.1.Behavior Linear Model42
    3.4.2.Transient Response45
    3.5.Measurement Environment Setup and Experiment Results47
    3.5.1.Concept47
    3.5.2.Measurement Environment Setup47
    3.5.3.Experiment Results49
    Chapter 4Wide-Range Synchronous Mirror Delay with Arbitrary Input Duty Cycle55
    4.1.Architecture of Conventional Synchronous Mirror Delays55
    4.1.1.Original Synchronous Mirror Delay55
    4.1.2.Interleaved Synchronous Mirror Delay57
    4.1.3.Direct-Skew-Detect Synchronous Mirror Delay58
    4.1.4.Mixed-mode Synchronous Mirror Delay59
    4.1.5.Successive Approximation Register Synchronous Mirror Delay60
    4.1.6.Arbitrary Duty Cycle Synchronous Mirror Delay61
    4.2.Wide-Range Synchronous Mirror Delay62
    4.2.1.Proposed SMD Architecture62
    4.2.2.Timing and Operation Analysis63
    4.3.System Analysis66
    4.3.1.Linear Model Analysis66
    4.3.2.Behavior Model Analysis68
    4.4.Simulation Results69
    Chapter 5Wide-Range Digital Clock Synchronous Buffer with Digitally Programmable Output Duty Cycle75
    5.1.Wide-Range Digital Clock Synchronous Buffer75
    5.1.1.Pulse Width Generator (PWG)79
    5.1.2.Multi-Band Delay Monitor Circuit (MB-DMC)80
    5.1.3.Measurement and Mirror Circuit (MMC)81
    5.1.4.Phase Compensation Circuit (PCC)82
    5.1.5.Frequency Phase Comparator (FPC)82
    5.1.6.Modified Pulse Width Control Loop (PWCL)85
    5.2.System Analysis and Simulation Results88
    5.2.1.Different Phase Alignment Comparison88
    5.2.2.Stage Length of Delay Line Analysis89
    5.2.3.Locking Time Analysis90
    5.2.4.Dynamic frequency hopping90
    5.2.5.Different Output Duty Cycle92
    5.2.6.Jitter Induced and Ground Bounce Simulation93
    5.3.Measurement Environment Setup and Experiment Results95
    5.3.1.Concept95
    5.3.2.Measurement Environment Setup95
    5.3.3.Experimental Results97
    Chapter 6Conclusions and Future Works103
    6.1.Conclusion103
    6.2.Future Work105
    Reference107
    Publication List113
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  • Kuo-Hsing Cheng(G꿳)
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    Date of Submission 2008-11-14

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