Title page for 90521050


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Student Number 90521050
Author Jue-Hao You(´åÀﻨ)
Author's Email Address No Public.
Statistics This thesis had been viewed 2597 times. Download 1947 times.
Department Electrical Engineering
Year 2002
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Clock Multiplier Unit and Data/Clock Recovery for OC-192 Transceiver
Date of Defense 2003-07-07
Page Count 125
Keyword
  • CDR
  • CMU
  • OC-192
  • transceiver
  • Abstract The optical network applies in the high-speed and long-haul communications has become a major trend presently. Today, the highest speed for wired data communication is reached using optical fiber transmission operating in accordance with the SONET (Synchronous Optical Networking Standards) standards. The data rate of the SONET OC-192 is close to 10Gb/s and it expects that the data rate of 10Gb/s will be universal in backbone network and applied in terminal networks. And the transceiver is the critical device in high-speed optical networks. The goal in the thesis is to develop a clock multiplier unit and clock/data recovery circuit that suit to the SNOCT OC-192 transceiver. At the transmitter end, the encoded parallel data must be transformed into serial signals by MUX and therefore a CMU is needed to generate a high-speed reference signal for parallel-to-serial data conversion and multiplexing. At the receiver end, a CDR circuit derives the input frequency and phase of the NRZ signals and generates a high precision clock to sample the incoming data so as to reduce the bit error rate.
      Clock multiplier Unit is accomplished by using PLL-based frequency synthesizer. The main goal is to generate a reference signal for multiplexer. Its function is to synthesize a 9.9533GHz output signal form a 622.08MHz reference source according to the SONET OC-192 standard. For various applications, the output frequency range of the oscillator covers that of various communication standards around 10Gb/s. The CMU circuit is fabricated in TSMC 0.35£gm BiCMOS process and its operation voltage is 3.3V. An individual chip of 16:1 static frequency divider has been designed and demonstrated. Its operation range is 500 MHz ~ 9.1 GHz, chip size is 1 ¡Ñ 0.8 mm2, and power consumption is 78.7mW. It can be used to generate down-frequency clock signals for demultiplexer and used in frequency synthesizer. A fully differential clock multiplier unit presented in the thesis achieves improved levels of phase noise and supply rejection performance through the use of fully differential architecture. The CMU has a die size of 2.1 ¡Ñ 1.1 mm2 and consumes 230.4mW from 3.3 V.
    PLL-based CDRs are benefited from capabilities of high frequency operation and feasibility for monolithic integration. Moreover, the phase frequency detector can adjust the transition edge of the sampling clock and align to that of the input data. Therefore, conventionally, high frequency clock and data recovery circuits are of PLL based type. A PLL-based high-speed CDR circuit without reference signals is achieved in this thesis. Because the phase detector used in the CDR is binary type, the conventional linear model of the PLL does not fit it. A novel analytical linear model for the binary type CDR circuit is addressed. Then a CDR circuit that conforms to the SONET OC-192 jitter requirements is designed by it. The CDR circuit is fabricated in TSMC 0.35£gm BiCMOS process and its operation voltage is 3.3V. The architecture of it is fully differential and the output frequency range covers that of various communication standards around 10Gb/s. Finally, the jitter bandwidth is 4.18MHz, jitter peaking is 0dB, and the jitter generation is about 5ps. The jitter performances of it suit the OC-192 jitter requirements and its power consumption is 589.1mW.
    Table of Content Content
    Abstracti
    Contentiii
    List of Figuresvii
    List of Tablesx
    Chapter 1Introduction1
    1.1Motivation1
    1.2Research Goals3
    1.3Thesis Organization5
    1.4References6
    Chapter 2Frequency Synthesizer and Clock/Data Recovery in Optical Fiber Systems8
    2.1Introduction8
    2.2Transmitter and Receiver Architecture9
    2.2.1Transmitter9
    2.2.2Receiver10
    2.3Frequency Synthesizer12
    2.3.1Role of Frequency Synthesizer12
    2.3.2Phase Noise13
    2.3.3Spurious Tones14
    2.4Clock and Data Recovery14
    2.4.1Role of Clock and Data Recovery15
    2.4.2PLL-Based CDR Circuit16
    2.4.3Over-sampling-Based Data Recovery17
    2.4.4Summary18
    2.5Summary19
    2.6Reference19
    Chapter 3A 10GHz Fully-Differential Frequency Synthesizer21
    3.1Introduction21
    3.2Phase Looked Loop Fundamentals22
    3.2.1Phase Locked Loop Fundamental22
    3.2.2Frequency Synthesizer Architecture23
    3.3PLL Linear Model24
    3.4Voltage-Controlled Voltage26
    3.4.1The principle of the LC-tank VCO27
    3.4.2Inductor28
    3.4.3Switching Tuning Mechanism29
    3.4.4VCO Topology and Simulation Results30
    3.516:1 Frequency Divider32
    3.5.1Two Types of the Digital Frequency Divider32
    3.5.2Design Method for Low Power Consumption33
    3.5.3Circuit Implementation36
    3.5.4Summary40
    3.6Other Circuitry Design41
    3.6.1Phase/Frequency Detector41
    3.6.2Charge Pump43
    3.6.3Loop Filter44
    3.6.4Output Buffer46
    3.6.5Bias Circuit46
    3.7Simulation and Experimental Results48
    3.7.1Chip Overview48
    3.7.2Simulation49
    3.7.3Layout51
    3.7.4Measurement Results53
    3.8Summary56
    3.9References57
    Chapter 4Jitter Analysis for PLL-Based CDR Circuit60
    4.1Introduction60
    4.2The Reasons for Jitter Production61
    4.2.1Noise61
    4.2.2Data Randomness61
    4.2.3Pattern-Dependant Jitter62
    4.3The Basic Jitter Requirement for SONET OC-19262
    4.3.1Jitter Generation63
    4.3.2Jitter Transfer63
    4.3.3Jitter Tolerance64
    4.4Jitter Analysis in Linear PLL-Based CDR65
    4.4.1Jitter Transfer Analysis65
    4.4.2Jitter Tolerance Theory and Analysis67
    4.4.3Jitter Generation76
    4.5Summary76
    4.6Reference76
    Chapter 5A 10Gb/s Clock and Data Recovery Circuit Without Frequency Acquisition78
    5.1Introduction78
    5.2Clock and Data Recovery Fundamentals79
    5.2.1The work of CDR in Receivers79
    5.2.2NRZ Data Input80
    5.2.3Phase-Locking CDR Architecture81
    5.3The CDR Architecture without Reference Clock83
    5.4Jitter Analysis for Binary CDR Loop84
    5.5Phase and Frequency Detector88
    5.5.1Phase/Frequency Detector Architecture88
    5.5.2The operation89
    5.5.3Circuit Design91
    5.5.4Simulation93
    5.6Other Circuitry Design94
    5.6.1Charge Pump and Loop Filter94
    5.6.2Quadrature-Phase VCO96
    5.6.3Input Buffer100
    5.6.4Output Buffer100
    5.6.5Decision Circuit and Bias Circuit101
    5.7Simulation Results102
    5.7.1Chip Overview102
    5.7.2Simulation104
    5.8Summary106
    5.9References107
    Chapter6Conclusion109
    6.1Conclusion109
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    Advisor
  • Chien-Nan Liu(¼B«Ø¨k)
  • Wei-Zen Chen(³¯ÄÞ¤¯)
  • Files
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    Date of Submission 2003-07-09

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