Title page for 89521079


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Student Number 89521079
Author Hung-Chin Ke(¬_§»¿Ë)
Author's Email Address No Public.
Statistics This thesis had been viewed 2902 times. Download 2009 times.
Department Electrical Engineering
Year 2001
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title IP reuse design and Verification for Advance Encryption Standard algorithm
Date of Defense 2002-06-04
Page Count 80
Keyword
  • AES
  • FPGA
  • Image encryption
  • IP
  • Reuse
  • Abstract In order to speed up the pace of system on a chip (SOC) development, designers intend to integrate intellectual properties (IP) into the chip. IP in chip design industry refers to pre-designed and pre-verified building blocks that can be reused for faster time-to-market. In this thesis, the research is focus on the characteristic of Advance Encryption Standard (AES). Using the IP reuse concept of AES to implement the 128bits block cipher efficiently and increase flexibility of Encryptor / Decryptor, we design Encryption Core and Decryption Core separately. Moreover, because the AES algorithm is the iterative encryption algorithm, we just only design one encryption/decryption architecture, pipeline architecture and using the feedback circuit to reduce the hardware complexity. In order to reduce the I/O pins, we design the shift register with four clocks cycles imports the Plaintext 128 bits and Secret Key 128 bits.
    To realize the AECs, we use VHDL, Synplify, ModelSim, and MaxplusII for designing, synthesizing and simulation. Field Programmable Gate Arrays (FPGAs) are chosen as our target hardware environment. The encryption core design of AECs for area requires 1437 logic cells. The maximum operating clock is 100Mhz and the corresponding data throughput is about 1163Mbit/s. the decryption core design of AECs for area requires 1895 logic cells. The maximum operating clock is 90Mhz and the corresponding data throughput is about 900Mbit/s. According to the characteristic, we can apply to the field of Image encryption.
    Table of Content Contents
                              
    Abstract ( In Chinese)              
    Abstract ( In English)
    List of Figures 
    List of Tables 
    Chapter 1  Introduction..........................1
    1.1Motivation.................1
    1.2Literature Survey........1
    1.3Aim of the Thesis.......2
    1.4Merit of the Method...2
    1.5Organization of the Thesis...3
    Chapter 2 Description of AES algorithm.....4
    2.1 General Description......4
    2.2 Definition and Notation.....4
      2.2.1 Glossary of Terms and Acronyms....5
      2.2.2 Algorithm Parameters, Symbols, Terms, and Functions...6
      2.2.3 Inputs and Outputs...7
      2.2.4 The state, the Cipher Key and the number of rounds..8
    2.3 Mathematical preliminaries.......10
      2.3.1 Galois Field.......10
      2.3.2 Polynomial Addition........10
      2.3.3 Polynomial Multiplication.....11
    2.3.4 Polynomial multiplication by x.........12
    2.4 Cipher......12
      2.4.1 ByteSub Transform......13
      2.4.2 ShiftRow Transform.....15 
      2.4.3 MixColumn Transform.....16
      2.4.4 AddRoundKey Transform.....17
    2.5 Key schedule......18
      2.5.1 Key expansion....18
      2.5.2 Key selection....20
    2.6 Inverse Cipher.......21
      2.6.1 InvBytesub transform.....21
      2.6.2 InvShiftRow transform.....21
      2.6.3 InvMixColumn transform....22
      2.6.4 AddRoundkey transform....22
    2.7 Summary......23
    Chapter 3 Implementation of the AES block cipher....25
    3.1 AES design strategy.....26
    3.2 FPGA architecture of AES block cipher....27
      3.2.1 The Encryption Core.........27
      3.2.1 The Decryption Core........29
    3.3 AES Finite State Machine (FSM) Controller......31
    3.4 Matlab Implementation of the AES......32
      3.4.1 The Cipher.......32
      3.4.2 The Inverse Cipher......33
      3.4.3 Key expansion.....34
    Chapter 4 Analysis and design of AES cipher main macro....35
    4.1 IP reuse introduction....35
    4.2 Analysis and design of AES cipher main macro....37
      4.2.1 Encryption macro...37
      4.2.2 Decryption macro....38
      4.2.3 Input/Output shift register unit....39
      4.2.4 ByteSub/InvByteSub unit design....41
      4.2.5 ShiftRow/InvShiftRow unit design ....42
      4.2.6 MixColumn/InvMixColumn unit design...44
      4.2.7 AddRoundkey unit design...47
      4.2.8 ERU and DRU unit design...47
      4.2.9 Key schedule unit design...48
    Chapter 5 IP reuse design and verification for AES cipher51
    5.1 Encryption/Decryption core block diagram....51
    5.2 Comprehensive technical specification.....53
    5.3 Core interface and Pins description....53
      5.3.1 AES interface....56
      5.3.2 AES controller...58
    5.4 Integration of key macro....59
    5.5 Cad tools and environment.....60
    5.6 AES timing simulation......62
    Chapter 6 Conclusion and Future work...69
    Bibliography....71
    Appendix A ¡V Altera Apex20KC device...73
    Appendix B ¡V Cipher Example....75
    Appendix C ¡V Matlab implementation of the AES cipher...77
    and inverse cipher
    Appendix D ¡V Enhancing Compression and Encryption.....81
    of image with FPGA-based Cryptosystems
    Reference BIBLIOGRAPHY
    [1] ¡§National Bureau of Standards ¡V Data Encryption Standard,¡¨ FIPS     Publication 46,1977.
    [2] M.Shand and J.Vuillemin, ¡§Fast Implementations of RSA Cryptography,¡¨ in Proceedings. 11th Symposium on Computer Arithemtic, pp. 252-9,1993.
    [3] Joan Daemen and Vincent Rijmen, AES Proposal: Rijndael, AES algorithm
    Submission, September 3, 1999, available at
    http:// csrc.nist.gov/publications/ /fips/fips197/fips-197.pdf
    [4] Michael Keating and Pierre Bricaud, ¡§Reuse Methodology Manual for system on a chip designs second edition,¡¨ May 1999.
    [5] J. Buchholz, ¡§Matlab implementation of AES standard,¡¨ November 29, 2001
    http://buchholz.hs-bremen.de.
    [6] Viktor Fischer, ¡§Realization of the Round 2 AES Candidates using Altera FPGA,¡¨ MICRONIC s. r. o., Dunajská 12, Košice, Slovakia.
      http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
    [7] P. Chodowiec, K. Gaj, ¡§Implementation of the Twofish Cipher Using FPGA Devices¡¨, Technical Report, George Mason University, July 1999.
    [8] Piotr Mrocozkowski, ¡§Implementation of the block cipher Rijndael using
    Altera FPGA¡¨, May, 2000 http://csrc.nist.gov/encryption/aes/round2/pubcmnts.htm
    [9] AES home page: http://www.nist.gov/aes/.
    [10] Hung Chin Ke,¡¨ Enhancing Compression and Encryption of image with FPGA-based Cryptosystems¡¨, Applied informatics international symposium on software engineering,databases, and applications, February 18-21,2002, Innsbruck,Austria, Page(s): 187-192.
    [11] B. Schneier, ¡§Applied Cryptography Second Edition,¡¨ John Wiley & Sons, 1996.
    [12] Altera Digital Library 2001.
    [13] Munteanu, A.; Cornelis, J.; Van Der Auwera, G.; Cristea, P.,¡¨ Wavelet image compression - the quadtree coding approach¡¨, Information Technology in Biomedicine, IEEE Transactions on , Volume: 3 Issue: 3 , Sept. 1999 Page(s): 176 ¡V185.
    [14] Bing-Bing Chai, Xinhua Zhuang, ¡¨Significance-Linked Connected Component Analysis for Wavelet Image Coding¡¨
    [15] Viktor Fischer, ¡§ Realization of the Round2 AES Candidate using Altera FPGA  http://csrc.nist.gov/encryption/aes/round2/conf3/aes3papers.html
    [16] James Nechvatal, et al., Report on the Development of the Advanced Encryption Standard (AES), National Institute of Standards and Technology.
    [17] Benjamin Leperchey,Charles Hymans, ¡§FPGA implementation of the Rijndael algorithm¡¨ June 16,2000.
    [18] A JAVA servlet implementation, by Cass Crockatt. , A Visual Basic implementation , by P. Fresle, An implementation in C++, by Gerhard Wesp.
    [19] The architecture of AES can be found, http://www.esat.kuleuven.ac.be/~rijmen/rijndael/
    [20] R. Rivest, A.Shamir, and L. Adleman, ¡¨ A method for obtaining digital signatures and public key cryptosystems,¡¨ Communications of the ACM, vol.21, no.2, pp.120-126, Feb.1978.
    [21] Philip P. Dang and Paul M.Chau, ¡¨Image encryption for secure internet multimedia applications ¡¨ Consumer Electronics, IEEE Transactions on, Volume: 46 Issue: 3, Aug. 2000 Page(s): 395 ¡V403.
    [22] Cheng, H.; Xiaobo Li,¡¨ Partial encryption of compressed images and videos¡¨ Signal Processing, IEEE Transactions on , Volume: 48 Issue: 8 , Aug. 2000 Page(s): 2439 ¡V2451.
    [23] X.Li,J.Knipe, and H.Cheng,¡¨ Image compression and encryption using tree structures, ¡¨Patt.Recogn.Lett.,vol.18,no.11-13,pp.1253-1259,Nov.1997.
    [24] C.E. Shannon, ¡§A Mathematical Theory of Communication¡¨, Bell system technical journal, vol.27, no.3, pp.379, 1948.
    [25] Shapiro, J.M.,¡¨ Embedded image coding using zerotrees of wavelet coefficients¡¨, Signal Processing, IEEE Transactions on , Volume: 41 Issue: 12 , Dec. 1993 Page(s): 3445 ¡V3462.
    [26] Zhong, J.M.; Leung, C.H.; Tang, Y.Y.,¡¨ Wavelet image coding based on significance extraction using morphological operations¡¨, Vision, Image and Signal Processing, IEE Proceedings- , Volume: 146 Issue: 4 , Aug. 1999 Page(s): 206 ¡V210.
    [27] Servetto, S.D.; Ramchandran, K.; Orchard, M.T.,¡¨ Wavelet based image coding via morphological prediction of significance¡¨, Image Processing, 1995. Proceedings., International Conference on , Volume: 1 , 1995 Page(s): 530 -533 vol.1.
    [28] Said, A.; Pearlman, W.A.,¡¨ A new, fast, and efficient image codec based on set partitioning in hierarchical trees¡¨, Circuits and Systems for Video Technology, IEEE Transactions on Volume: 6 Issue: 3 , June 1996 Page(s): 243 ¡V250.
    [29] Jan-Ruei Lin, ¡§Design of Encryption Chips Using the Blowfish Algorithm,¡¨ Master Thesis, Central University, 2000.
    [30] Pei-Jung Wu¡§VLSI Implementation and IP Design for Advanced Encryption standard¡¨,Master Thesis, Tung Hwa University 2001.
    [31] Yeh, Bi-Yun, ¡§IP-Based Chip Design Methodology¡¨,Matster Thesis, Taiwan University,1996
    Advisor
  • Shih-Ching Ou(¼Ú¥ÛÃè)
  • Files
  • 89521079.pdf
  • approve immediately
    Date of Submission 2002-06-05

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