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Student Number 89521017 Author Chien-Liang Kuo(³¢«Ø¨}) Author's Email Address ee892017@ee.ncu.edu.tw Statistics This thesis had been viewed 3200 times. Download 3349 times. Department Electrical Engineering Year 2001 Semester 2 Degree Master Type of Document Master's Thesis Language English Title A 1.8V¡A10GHz CMOS Frequency Synthesizer Date of Defense 2002-07-05 Page Count 76 Keyword divider frequency synthesizer PLL Abstract The fully integrated frequency synthesizer fabricated in TSMC 0.18um CMOS technology is presented. It is capable of using in SONET (Synchronous Optical Network) OC (Optical Carrier)-192 transceiver system and also RF receiver. This frequency synthesizer adopted a monolithic VCO (Voltage Control Oscillator) with quadrature phase outputs, which oscillates around 10GHz. In its feedback path the divider is used for multiply the input reference clock. This design the multi-modulus divider can change its divisor from 512 to 519. (or just 16 for OC-192) which capable of operating around 10GHz. For such operating frequency, the ILFD (Injection Locked Frequency Divider) technique is used in the prescaler in order to approach low power design for multi-modulus divider. This frequency synthesizer operates from 9.8GHz to 10.3GHz with single 1.8v supply and consumes 85 mW. The design theory, consideration, simulation and layout will be showing as the following.

A classical digital PLL architecture, which applies for RF system incorporating a digital divider in the feedback path for frequency multiplication, enables the function of channel selection or sigma delta modulation. Although, for the OC-192 it is divide by 16, this thesis proposed prescaler which capable of operating at 10 GHz with continuous output divide ratio. So, the design also focuses on high-speed prescaler, in order to breakthrough the circuit limitation as well as operating frequency. This thesis also proposed the ring oscillator based ILFD which fabricated on TSMC 0.25um CMOS process operating. The modulo-3 and modulo-5 ILFD operated on 7.1GHz and 18.1GHz respectively is also proposed and measured.Table of Content Content

Abstract1

Content2

List of Figures4

Chapter 1Introduction1

1.1Introduction1

1.2Thesis Organization4

Chapter 2PFD¡BCharge Pump and Loop Filter5

2.1Phase Frequency Detector5

2.1.1Basic Phase Frequency Detector5

2.1.2Reformed PFD6

2.2Charge Pump8

Chapter 3Voltage Control Oscillator11

3.1General Considerations12

3.2Phase noise13

3.2.1Leeson¡¦s Formula14

3.2.1.1Q of an oscillator14

3.2.1.2Phase Noise Mechanisms19

3.2.1.3Waveform Symmetry Properties21

3.3Dual Loop LC-VCO22

3.4Switched Tuning Technique24

3.5VCO Schematic30

3.6Simulation Result31

Chapter 4Multi-Modulus Divider32

4.1Architectural Approach32

4.2Prescaler34

4.2.1Introduction34

4.2.2Superharmonic ILFD35

4.2.2.1Introduction36

4.2.2.2Injection locked frequency divider architecture38

4.2.2.3Modulo-3 Frequency Divider40

4.2.2.4Modulo-5 Frequency Divider41

4.2.2.5Experimental results42

4.2.2.6Modulo-4 Frequency Divider50

4.2.3High Divide Ratio Multi-Phase ILFD51

4.2.4Phase Rotate Mechanism53

4.3Programmable Counter and Swallow Counter57

Chapter 5Conclusion59

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