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Student Number 89521007
Author Shi-Dai Mai(³Á¥@¹F)
Author's Email Address maxsida@ms27.hinet.net
Statistics This thesis had been viewed 2601 times. Download 368 times.
Department Electrical Engineering
Year 2001
Semester 2
Degree Master
Type of Document Master's Thesis
Language English
Title Multi-module synchronization methodology
Date of Defense 2002-07-05
Page Count 67
Keyword
  • ATE
  • PLL
  • synchronization
  • Abstract In this thesis, we propose two novel multi-module synchronization mechanisms. The first architecture describes a board level multiple modules synchronization. The second architecture describes an on-chip multiple modules synchronization. The two techniques target the synchronization for test channels in automatic test equipment (ATE) and system on a chip (SOC) environment respectively. We utilize fine tune mechanisms to suppress timing skews between modules and provide the highly stable phase. Both multi-module synchronization are based on TSMC 0.35 µm 1P4M CMOS and TSMC 0.18 µm 1P6M CMOS processes respectively. The results are at 200MHz and 1GHz respectively. The measurement and simulation results show that on-board architecture is capable of reducing the skew of the five modules to less than 100ps and the clock frequency up to 200MHz with 50ps clock jitter when the initial skew of each module is as large as 800ps. The simulation results also show that on-chip architecture reduces the skew of the five modules to less than 80ps and the clock frequency up to 1GHz with 20ps clock jitter when the initial skew of each module is as large as 800ps
    Table of Content CHAPTER 1INTRODUCTION1
    1.1MOTIVATION1
    1.2SURVEY OF THE TIMING GENERATION AND MEASUREMENT2
    1.3A DYNAMIC CLOCK DISTRIBUTION TECHNIQUE5
    1.4THESIS ORGANIZATION6
    CHAPTER 2 THE ARCHITECTURE OVERVIEW8
    2.1OVERVIEW8
    2.2MULTI-MODULE SYNCHRONIZATION MECHANISM10
    2.3THE SYNCHRONOUS DIGITAL CONTROL LOGIC12
    2.3.1PN FRAME DETECTION FSM CIRCUIT14
    2.3.2DATA EXTRACTION CIRCUIT14
    2.3.3LEAD/LAG PHASE DETECTION WITH PN SEQUENCE15
    2.3.4PN GENERATION16
    2.3.5PHASE ADJUSTMENT CIRCUIT16
    2.3.6ADDRESS DECODER17
    2.4THEORETICAL ANALYSIS OF THE PHASE DETECTION18
    CHAPTER 3ON-CHIP MULTI-MODULE SYNCHRONIZATION21
    3.1OVERVIEW21
    3.2THE LINEAR MODEL OF THE PLL23
    3.3THE CIRCUIT DESIGN OF THE PHASE LOCK LOOPS25
    3.3.1PHASE FREQUENCY DETECTOR25
    3.3.2CHARGE PUMP27
    3.3.3LOOP FILTER28
    3.3.4VOLTAGE CONTROLLED OSCILLATOR29
    3.3.5FREQUENCY DIVIDER32
    3.4NOISE ANALYSIS IN PLL CIRCUIT33
    3.5MULTI-MODULE SYNCHRONIZATION MECHANISM36
    CHAPTER 4SIMULATION AND MEASUREMENT RESULT45
    4.1DESIGN FLOW OF MULTI-MODULES SYNCHRONIZATION45
    4.2THE SIMULATION OF MULTI-MODULE SYNCHRONIZATION47
    4.3THE IMPLEMENTATION OF MULTI-MODULES SYNCHRONIZATION49
    4.4THE MEASUREMENT OF SYNCHRONIZATION MODULE51
    4.4.1THE MEASUREMENT OF THE SINGLE MODULE52
    4.4.2THE MEASUREMENT OF THE MULTI-MODULE SYSTEM56
    4.5THE SIMULATION OF THE ON-CHIP MULTIPLE MODULES59
    CHAPTER 5CONCLUSION63
    BIBLIOGRAPHY64
    Reference [1] D. F. Wann and M. A. Fanklin, ¡§Asynchronous and clocked control structures for VLSI based interconnections networks,¡¨ IEEE Trans. Computer., pp. 284-293, Mar. 1983.
    [2] Ting-Hai Chao et al., ¡§Zero skew clock net routing ,¡¨ 29th ACM/IEEE Design Automat. Conf. Digest Tech. Paper. pp. 518-523, 1992.
    [3] F. Minami and M. Takano, ¡§Clock tree synthesis based on RC delay balancing,¡¨ IEEE 1992 Custom Integrated Circuits Conf. Computer-Aided Digest of Tech. pp28.3.1-28.3.4, 1992.
    [4] Ren-Song Tsay, ¡§Exact zero skew,¡¨ in IEEE Intl. Conf. Comput.-Aided Design Digest Tech. Papers, pp. 336-339, 1991.
    [5] S. Boon et. al., ¡§High performance clock distribution for CMOS ASICs,¡¨ in IEEE 1989 Custom Integrated Circuits Conf. Computer-Aided Digest of Tech. pp15.4.1-15.4.5, 1989.
    [6] F. Minami, and M. Takano, ¡§Clock tree synthesis based on RC delay balancing¡¨ IEEE 1992 Custom Integrated Circuits Conference. Digest of Tech. Papers, 1992, pp: 28.3.1-28.3.4.
    [7] Ramanathan, P., Dupont, A.J., Shin, K.G. ¡§clock distribution in general VLSI circuits¡¨, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on , Volume: 41 Issue: 5 , May 1994, pp: 395 -404
    [8] Joon-Seo Yim, Seong-Ok Bae, Chong-Min Kyung, ¡§A floorplan-based planning methodology for power and clock distribution in ASICs¡¨, Design Automation Conference, 1999. Proceedings. 36th , 1999 pp: 766 -771
    [9] Ren-Song Tsay, ¡§Exact zero skew,¡¨ in IEEE Intl. Conf. Computer-Aided Design Digest Tech. Papers, 1991, pp: 336-339
    [10] Hyun Lee, Han Quang Nguyen, Potter, D.W. ¡¨Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback¡¨ ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International , 2000
    [11] Brueske, D.E., Embabi, S.H.K. ¡§A dynamic clock synchronization technique for large systems¡¨ Components, Packaging, and Manufacturing Technology, Part B, Volume: 17 Issue: 3 , Aug. 1994 pp: 350 -361
    [12] Mark Burns, Gordon W.Roberts. An Introduction to Mixed-Signal IC Test and Measurement, OXFORD university press, 2001
    [13] Restle, P.J., Deutsch, A. ¡§Design the best clock distribution network¡¨, VLSI Circuits. Digest of Technical Papers. 1998 Symposium, 1998 pp(s): 2 -5
    [14] S. Boon et. al, ¡§High performance clock distribution for CMOS ASICs,¡¨ in IEEE 1989 Custom Integrated Circuits Conference. Digest Tech. Papers. pp: 15.4.1-15.4.5.
    [15] Pangjun, J. Sapatnekar, S.S. ¡§Clock distribution using multiple voltage,¡¨ Proc. Int¡¦l Symp. Of Low Power Electronics and Design, 1999, pp. 145-150.
    [16] Taylor, G.. F., Geannopoulos, G. ¡§Microprocessor clock distribution,¡¨ IEEE 5th Technical Meeting on Electrical Performance of Electronic Packaging, 1996, pp29. 
    [17] S. F. Dow, J. M. Flasck and M. E. Levi, ¡§A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Convert Chip,¡¨ IEEE Transaction on Nuclear Science, vol. 43, Jam. 1996
    [18] Roland E. Best, Phase-Locked Loops: Theory, Design, and Applications, McGraw-Hill Inc., 2nd ed., 1993
    [19] Behzad Razavi, ¡§Monolithic Phase-Locked Loops and Clock Recovery Circuits¡¨, pp. 1-39, IEEE Press, 1996.
    [20] I. A. Young. ¡§A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessor,¡¨ IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp 1599-1607, Nov. 1992.
    [21] L. Kyoohyun, ¡§A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization,¡¨ IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp 807-815, June. 2000.
    [22] V. V. Kaenel. ¡§A 320MHz, 1.5mW @ 1.35V CMOS PLL for microprocessor Clock Generation ¡¨ IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp 1715-1722, Nov. 1996.
    [23] H. Notani, ¡§A 622-MHz CMOS Phaes-Locked Loop with Precharge-type Phase Frequency Detector, ¡¨ in Symposium on VLSI Circuits, Dig. Tech. Papers, pp 129-130, June 1994
    [24] M. Mizuno. ¡§A 0.18um CMOS Hot-Standby Phase-Locked Loop Using a Noise-Immune Adaptive-Gain Voltage-Controlled Oscillator,¡¨ in ISSCC Dig. Tech. Papers, pp 268-269, Feb. 1995.
    [25] John G. Maneatis. ¡§Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,¡¨ IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp 1723-1732, Nov. 1996.
    [26] Won-Hyo Lee ¡§A High Speed and Low Power Phase-Frequency Detector and Charge-pump¡¨ Proceedings of the ASP-DAC '99. Asia and South Pacific ,
    vol. 1, pp 269 -272 1999.
    [27] Lizhong Sun, ¡§A 1.25-GHz 0.35um Monolithic CMOS PLL Based on Multiphase Ring Oscillator,¡¨ IEEE Journal of Solid-State Circuits, vol. 36, no. 6, pp 1723-1732, JUNE. 2001.
    [28] K. B. Kim, D. Helman, and P. Gray, ¡§A 30-MHz hybrid analog-digital clock recovery circuit in 2-um CMOS,¡¨ IEEE Journal of Solid-State Circuits, vol. 25, pp 1385-1394, Dec. 1990.
    [29] S.K.Enam and A. Abidi, ¡§NMOS ICs for clock and data regeneration in gigabit-per-second optical-fiber receivers,¡¨ IEEE Journal of Solid-State Circuits, vol. 27, pp 1763-1774, Dec. 1992.
    [30] Koichiro Minami ¡§A 0.10um CMOS, 1.2V, 2GHz Phase-Locked Loop with Gain Compensation VCO¡¨ IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp 213-216, 2001
    [31] J. Yuan and C. Svensson, ¡§high speed CMOS circuit technique,¡¨ IEEE Journal of Solid-State Circuits, vol. 24, pp 62-70, 1989
    [32] William B. Wilson, Un-Ku Moon, Kadaba R.Lakshmikumar, Liang Dai. ¡§A CMOS Self-Calibrating Frequency Synthesizer,¡¨ IEEE Journal of Solid-State Circuits, 2000
    Advisor
  • Chau-Chin Su(Ĭ´Âµ^)
  • Files
  • 89521007.pdf
  • approve in 2 years
    Date of Submission 2002-07-08

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