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Student Number 88521074
Author Chun-Cheng Kuo(T)
Author's Email Address No Public.
Statistics This thesis had been viewed 1694 times. Download 850 times.
Department Electrical Engineering
Year 2000
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title Data Recovery Using Oversampling Technique and Its Application in USB2
Date of Defense 2001-06-21
Page Count 57
Keyword
  • data recovery
  • high speed
  • link
  • oversampling
  • USB
  • Abstract Recently, because of the multimedia applications the bandwidth requirement is increased. The serial bus is primary transmission media result in cost. How to transmit the most data in the limited channel becomes a great problem. Data recovery in the receiver also faces this problem. The traditional Phase Locked Loop based data recovery is not suitable for high-speed applications because of the process limitation.
    In this thesis, we will implement the high-speed mode data recovery of Universal Serial Bus and its speed is up to 480Mb/s. The concept of the data recovery will be introduce first. We choose CMOS process for its better integrity than GaAs and BiCMOS. Final the data recovery of the USB uses the oversampling circuit architecture. We proposed the elastically buffer architecture used to handle the underflow or overflow problem, which is caused by the frequency offset of transmitter and receiver. Its regular architecture is helpful in hardware implementation. The relationship of the buffer size and latency is also provided. The overall circuits implement in tSMC 0.35um 1P4M digital process. The performance of the data recovery can reach 625MHz and 15 bits overflow or 16 bits underflow can be deal with.
    Table of Content Chapter 1 Introduction1
    1.1Introduction of High-Speed Link1
    1.2Motivation2
    1.3Thesis Organization4
    Chapter 2 Overview of USB2 Specifications5
    2.1Introduction5
    2.1.1USB2 System Description6
    2.1.2USB2 Physical Interface7
    2.1.3Overview of USB2 Transceiver8
    2.2Specification of USB2 Data Recovery9
    2.3Summary11
    Chapter 3 Data Recovery12
    3.1Introduction12
    3.2Clock and Timing Recovery12
    3.3Serial Link Transceiver Architecture15
    3.3.1Clock Recovery using PLL18
    3.3.2Data Recovery using Oversampling19
    3.4Summary21
    Chapter 4 Oversampling Circuit Design22
    4.1Introduction22
    4.2Oversampling Design Problem23
    4.2.1Initial Synchronization23
    4.2.2Frequency Offset24
    4.3Oversampling Ratio25
    4.4Oversampling Design Techniques27
    4.4.13-phase DLL28
    4.4.2Sampling Block29
    4.4.3Sliding Window29
    4.4.4Transition Detector and Optimal Phase Decision30
    4.4.5Center Peaking and Majority Vote32
    4.4.6Elastically Buffer33
    4.4.7Preamble40
    4.4.8Timing of Overall Design41
    4.5Simulation Results42
    4.6Implementation Results43
    4.7Test Consideration46
    4.8Summary47
    Chapter 5 Oversampling Circuits in High Speed System48
    5.1Introduction48
    5.2Differential Current Switch Logic48
    5.3Oversampler51
    Chapter 6 Conclusions54
    Reference [1] Chih-Kong Ken Yang, F. R. Ramin and M.A. Horowitz, A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling Solid-State Circuits, IEEE J. Solid-State Circuits, vol.33, No.5, pp.713 X722, May. 1998.
    [2] Chih-Kong Ken Yang and M.A. Horowitz, A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links, IEEE J. Solid-State Circuits, vol.31, No.12, pp.2015 X2023, Dec. 1996.
    [3] K. Lee, S. Kim, G. Ahn and D. K. Jeong, A CMOS serial link for fully duplexed data communication, IEEE J. Solid-State Circuits, vol.30, No.4, pp.353 X364, April. 1995.
    [4] S. Kim, K. Lee, D. K. Jeong, D. D. Lee and A.G. Nowatzyk, An 800 Mbps multi-channel CMOS serial link with 3/spl times/ oversampling, Custom Integrated Circuits Conference, 1995, pp.451 X455.
    [5] USB Implementers Forum web page at http://www.usb.org.
    [6] R. D. Chiao, The Low Noise Output Buffer Design Techniques and Clock Recovery Implementation for USB2 Physcial Layer, M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 2000.
    [7] S. H. Kuo, The Low Noise Output Buffer Design Techniques and Transceiver Implementation for USB2 Physical Layer, M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 2000.
    [8] M. C. Chang, The Design and Application of Self-Biased Delay-Locked Loop, M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, June 1999.
    [9] Universal Serial Bus specification revision 2.0, Mar. 2000.
    [10] K. Lee, Y. Shin, S. Kim, D. K. Jeong, G. Kim, B. Kim and D. V. Costa, 1.04 GBd low EMI digital video interface system using small swing serial link technique, IEEE J. Solid-State Circuits, vol.33, No.5, pp.816 X823, May. 1998.
    [11] M. Fukaishi, K. Nakamura, M. Sato, Y. Tsutsui, S. Kishi and M. Yotsuyanagi, A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture, IEEE J. Solid-State Circuits, vol.33, No.12, pp.2139 X2147, Dec. 1998.
    [12] B. Sklar, Digital Communications, Englewood Cliffs, PTR Prentice Hall, 1998
    [13] D. Somasekhar and K. Roy, Differential current switch logic: a low power DCVS logic family, IEEE J. Solid-State Circuits, vol.31, No.7, pp.981 X991, July. 1996.
    [14] IEEE Std 1394b-2000: IEEE standard for a high perf
    [15] RAMBus specification Version 1.11, July. 2000
    [16] IEEE Std 803.2: IEEE standard for 1000Mbps Ethernet
    Advisor
  • Shyh-Jye Jou(P@)
  • Files
  • 88521074.pdf
  • approve in 2 years
    Date of Submission 2001-06-21

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