Student Number 88521074 Author Chun-Cheng Kuo(³¢«T¸Û) Author's Email Address No Public. Statistics This thesis had been viewed 1748 times. Download 880 times. Department Electrical Engineering Year 2000 Semester 2 Degree Master Type of Document Master's Thesis Language zh-TW.Big5 Chinese Title Data Recovery Using Oversampling Technique and Its Application in USB2 Date of Defense 2001-06-21 Page Count 57 Keyword data recovery high speed link oversampling USB Abstract Recently, because of the multimedia applications the bandwidth requirement is increased. The serial bus is primary transmission media result in cost. How to transmit the most data in the limited channel becomes a great problem. Data recovery in the receiver also faces this problem. The traditional Phase Locked Loop based data recovery is not suitable for high-speed applications because of the process limitation.
In this thesis, we will implement the high-speed mode data recovery of Universal Serial Bus and its speed is up to 480Mb/s. The concept of the data recovery will be introduce first. We choose CMOS process for its better integrity than GaAs and BiCMOS. Final the data recovery of the USB uses the oversampling circuit architecture. We proposed the elastically buffer architecture used to handle the underflow or overflow problem, which is caused by the frequency offset of transmitter and receiver. Its regular architecture is helpful in hardware implementation. The relationship of the buffer size and latency is also provided. The overall circuits implement in tSMC 0.35um 1P4M digital process. The performance of the data recovery can reach 625MHz and 15 bits overflow or 16 bits underflow can be deal with.
Table of Content Chapter 1 Introduction1
1.1Introduction of High-Speed Link1
Chapter 2 Overview of USB2 Specifications5
2.1.1USB2 System Description6
2.1.2USB2 Physical Interface7
2.1.3Overview of USB2 Transceiver8
2.2Specification of USB2 Data Recovery9
Chapter 3 Data Recovery12
3.2Clock and Timing Recovery12
3.3Serial Link Transceiver Architecture15
3.3.1Clock Recovery using PLL18
3.3.2Data Recovery using Oversampling19
Chapter 4 Oversampling Circuit Design22
4.2Oversampling Design Problem23
4.4Oversampling Design Techniques27
4.4.4Transition Detector and Optimal Phase Decision30
4.4.5Center Peaking and Majority Vote32
4.4.8Timing of Overall Design41
Chapter 5 Oversampling Circuits in High Speed System48
5.2Differential Current Switch Logic48
Chapter 6 Conclusions54
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Advisor Shyh-Jye Jou(©P¥@³Ç)
approve in 2 years
88521074.pdf Date of Submission 2001-06-21