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Student Number 87324022
Author Chin-Wei Kuo(³¢®ÊÞ³)
Author's Email Address cwkuo@ee.ncu.edu.tw
Statistics This thesis had been viewed 3328 times. Download 1940 times.
Department Electrical Engineering
Year 2003
Semester 1
Degree Ph.D.
Type of Document Doctoral Dissertation
Language English
Title The large-signal model of complementary MOSFETs and its applications in high speed communication circuits
Date of Defense 2003-09-26
Page Count 120
Keyword
  • large-signal model
  • MOSFET
  • power contour
  • Abstract In near decades, the rapid growth of optical and wireless communication systems market drive optical and radio frequency integrated circuits into a higher level integration with lower power consumption. To achieve these goals, the designers have to integrate the discrete circuits on the same substrate to reduce the size and the cost. However, with the scaling down of the CMOS channel length into deep sub-micrometer scale, the characteristic of CMOS device could be improved for GHz application.
    In the chapter 2, this thesis survey the modified MOSFET RF large-signal model in 0.18 mm CMOS technologies for optical and the RF circuits design. The modified large-signal model consists of a conventional BSM3v3 model and the passive networks which represent the parasistic effects of the MOSFET.
    In the chapter 3, this study proposed a self-define large-signal model for 50 mm-wide nMOS transistor. The self-defined model can predict not only dc and microwave performance well but also in noise characteristics by using P, R, C noise parameters calculation. In this empirical model, all the parameters were extracted from measurement results; moreover, the intrinsic parameters could be characterized as functions of the gate to source voltage (Vgsi) and drain to source voltage (Vdsi).
    Moreover, in the chapter 4, various RF circuits are presented based on the modified RF large-signal model described in the chapter 2. The RF circuits include a 2.4 GHz voltage-controlled oscillator, a 2.4 GHz low-noise amplifier, a double-balanced mixer and a 2.4 GHz down-converter. Most of the circuits use the MOSFET RF large-signal model described in the chapter 2. The voltage-controlled oscillator delivered ¡V5 dBm to 4 dBm as the oscillated frequency moved from 2.34 GHz to 2.45 GHz, which resulted in a tuning factor of 183 MHz/V. Furthermore, the phase noise of the VCO is ¡V110 dBc/Hz with a 1MHz offset at 2.4 GHz operation. Besides, the 2.4 GHz low-noise amplifier with common-source inductive degeneration architecture was presented. The LNA has the power gain of 14 dB at 2.4 GHz with a Fmin of 2.1 dB; as to the linearity behaviors, the P1dB and and the IIP3 of the LNA are ¡V4 dBm and 0 dBm, respectively. Moreover, the double-balance Gilbert cell mixer was introduce for the down-conversion application, the mixer provide the conversion of 3 dB with a P1dB of ¡V5 dBm; the RF-to-IF isolations are all greater than 18 dB and the LO-to-IF isolation can achieve 33 dB. As to the consideration of linearity, the IP3 of the mixer is located at input power of 0 dBm. At the last, a 2.4 GHz down-converter was proposed, which converts the 2.45 GHz RF signal to 80 MHz IF signal with the conversion of 12 dB and consuming 80 mW of DC power. Also, the P1dB and IIP3 of the CMOS down-converter is ¡V12 dBm and ¡V2 dBm.
    In the chapter 5, the optical transimpedance amplifiers and one stage limiting amplifier were presented. Here we used two peaking mechanisms for the TIA design namely, capacitive peaking and inductive peaking. In the TIAs design with the capacitive peaking approach, the 3 dB bandwidth can be enhanced from 875 MHz to 1.35 GHz without sacrificing its low-frequency gain. As to the inductive peaking design, both gate-inductive peaking and drain inductive peaking were presented in this chapter. By using the gate and drain inductive peaking approach, the 3-dB bandwidth could be improved from 4.4 GHz to 6.8 GHz and from 4.4 GHz to 6.8 GHz, however, the drain-inductive peaking demonstrated the superior characteristics in the output eye patterns. On the part of limiting amplifier, a one stage LA for 7 Gbps application was fabricated and characterized with the fully differential topology, which has the power gain of 13.8 dB and the 3 dB bandwidth can up to 4.4 GHz.
    Table of Content TABLE OF CONTENTS
    Abstract                                  I
    Figure captions                             VIII
    Table captions                              XIII
    Chapter 1 Introductions
    1-1. Motivation                               1
    1-2. Thesis Organization                          2 
    Chapter 2 The Modified MOSFET Scaleable RF Large-Signal Model
    2-1. Introduction                              4
    2-2. MOSFET Device Layout                          5
    2-3. Scaleable RF Large-Signal Model for 0.18-mm MOSFETs          8
    2-4. Passive Component Models                       22
      2-4-1. The equivalent circuit model of spiral inductors                                 22
    2-4-2. The equivalent circuit model of MIM capacitors             26
    2-5. Summary                                28
    Chapter 3 The Self-Defined Empirical MOSFER RF Large-Signal Model
    3-1. Introduction                              29
    3-2. MOSFET Large-Signal Model and Parameter Extraction                                 30
      3-2-1 The extractions of the DC-related parameters and I-V prediction                                 31
      3-2-2 The extractions of the extrinsic components                                 33
      3-2-3 The microwave and power performance prediction                                 35
    3-3. The prediction of noise performance                                39
      3-3-1 Parameters of the thermal noise                                   39
      3-3-2 High frequency noise model of nMOSFET              41
    3-4. The design of Low noise amplifier with different models                                   42
    3-5. Summary                                46
    Chapter 4 CMOS RF Circuits Design
      4-1.Introduction                            47
    4-2. The Microwave Voltage-Controlled Oscillators                                49
        4-2-1 Basic concept of the cross-coupled oscillator                                 49
        4-2-2 The 2.4 GHz Monolithic CMOS voltage-controlled oscillator                                 52
    4-3. The Microwave Low-Noise Amplifier                   56
    4-3-1 Basic concept of the LNA                                    56
    4-3-2 Topologies of the LNA                                    57
        4-3-3 The 2.4 GHz low-noise amplifier design                                 61
      4-4. The Microwave Gilbert-Cell Mixer                                   62
    4-4-1 Basic concept of the Gilbert-cell mixer                                   66
    4-4-2 The Monolithic CMOS double-balanced Gilbert-cell Mixer                                   67
    4-5. The Microwave Down-Converter                                 72
        4-5-1 The architecture of the 2.4 GHz CMOS down-converter                                 72
        4-5-2 The architecture of the 2.4 GHz CMOS down-converter                                 72
      4-6. Summary                               77
    Chapter 5 CMOS Integrated Circuits for Optical Communications
      5-1. Introduction                               78
    5-2. The Design of Transimpedance Amplifier                                 79
        5-2-1 The TIA design with the capacitive peaking mechanism                                 80
        5-2-2 The TIA design with the inductive peaking mechanism                                 86
    5-3. The Design of limiting Amplifier                                 102
    5-3-1 The technique of broadband design in limiting amplifier                                 102
    5-3-2 The design of the limiting amplifier                                 104
        5-3-3 The experimental results                                  105
      5-4. Summary                               108
    Chapter 6 Conclusions                            109
    Bibliongraphy                                111
    Publication List                                118
    Reference Bibliography
    [1] M. Saito, M. Ono, R. Fujimono, H. animoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose and H. Iwai, ¡§0.15 mm RF CMOS technology compatible with logic CMOS for low-voltage operation¡¨, IEEE Trans. on Electron Devices, vol. 45, pp. 737-742, Mar. 1998.
    [2] A. E. Schmitz, R. H. Walden; L. E. Larson; S. E. Rosenbaum; R. A. Metzger and J.R. Behnke, ¡§A deep-submicrometer microwave/digital CMOS/SOS technology¡¨, IEEE Electron Device Letters, vol. 12, pp. 16-17, Jan. 1991.
    [3] J. Moers, D. Klaes, A. Tonnesmann, L. Vescan, S. Wickenhauser, M. Marso, P. Kordos and H. Luth, ¡§19 GHz vertical Si p-channel MOSFET¡¨, IEE Electronics Letters, vol. 35, pp. 239-240, Feb. 1999.
    [4] A. I. A. Cunha, M. C. Schneider and C. G. Montoro, ¡§An MOS transistor model for analog circuit design¡¨, IEEE Journal of Solid-State Circuits, vol. 33, pp. 1510-1519. Oct. 1998.
    [5] C. Enz, ¡§MOS transistor modeling for RF integrated circuit design¡¨, in Proc. Custom Integrated Circuits Conference (CICC), pp. 189-196, May 2000.
    [6] C. H. Kim, C. S. Kim, H. K. Yu and K. S. Nam, ¡§Unique extraction of substrate parameters of common-source MOSFETs¡¨, IEEE Microwave and Guided Wave Letters, vol. 9, pp. 108-110, Mar. 1999.
    [7] Y. Cheng and M. Matloubian, ¡§On the high-frequency characteristics of substrate resistance in RF MOSFETs¡¨, IEEE Electron Device Letters, vol. 21, pp. 604-606, Dec. 2000.
    [8] M. Kittler, F. Schwierz and D. Schipanski, ¡§Scaling of the vertical and lateral MOSFETs in the deep submicrometer range¡¨, in Proc. Int. Caracas Conference on Devices, Circuits and Systems, pp. D58/1-D58/6, 2000.
    [9] R. H. Yan, K. F. Lee, D. Y. Jeon, Y. O. Kim, B. G. Park, M. R. Pinto, et al. ¡§High performance 0.1 mm room temperature Si MOSFETs¡¨, in Technical Digest of VLSI Technology, pp. 86-86, June 1992.
    [10] R. H. Yan, K. F. Lee, D. Y. Jeon, Y. O. Kim, B. G. Park, M. R. Pinto, et al. ¡§89 GHz ft room-temperature silicon MOSFETs¡¨, IEEE Electron Device Letter, vol. 13, pp. 256-258, May 1992.
    [11] W. Liu, R. Gharpurey, M. C. Chang, U. Erdogan, R. Aggarwal and J. P. Mattia, ¡§RF MOSFET modeling accounting for distributed substrate and channel resistances with emphasis on the BSIM3v3 SPICE model¡¨, in Technical Digest of Electron Devices Meeting, pp. 309¡V312, 1997.
    [12] J. J. Ou, X. Jin, I. Ma, C. Hu and P. R. Gray, ¡§CMOS RF modeling for GHz communication IC¡¦s¡¨, in Technical Digest of VLSI Technology, pp. 94-95, 1998.
    [13] A. Ferrero, V. Teppati and A. Carullo, ¡§Accuracy evaluation of on-wafer load-pull measurements¡¨, IEEE Trans. on Microwave Theory and Techniques, vol. 49, pp. 39-43, Jan. 2001.
    [14] M. Demmler, B. Hughes and A. Cognata, ¡§ A 0.5-50 GHz on-wafer, intermodulation, load-pull and power measurement system¡¨, in Techical Digest of IEEE MTT-S Symposium, vol. 3, pp. 1041-1044, May 1995.
    [15] F. Deshours, E. Bergeault, F. Blache, J. P. Villotte and B. Villeforceix, ¡§Experimental comparison of load-pull measurement systems for nonlinear power transistor characterization¡¨, IEEE Trans. on Instrumentation and Measurement, vol. 46, pp. 1251-1255, Dec. 1997.
    [16] M. C. Ho, K. Green, R. Culbertson, J. Y. Yang D. Ladwig and P. Ehnis,¡¨A physical large signal si MOSFET model for RF circuit design¡¨, in Techical Digest of IEEE MTT-S Symposium, vol. 2, pp. 391-394, June 1997.
    [17] BSIM3v3 manual, Department of electrical Engineering and Computer Sciences, University of California, Berkeley, 1996.
    [18] S. Lee and H. K. Yu, ¡§A semianalytical parameter extraction of a SPICE BSIM3v3 for RF silicon MOSFETs using S-parameter¡¨, IEEE Trans. on Microwave Theory and Techniques, vol. 48, pp. 412-416, Feb. 2000.
    [19]S. Lee and H. K. Yu, ¡§A new extraction method for BSIM3v3 model parameters of RF silicon MOSFETs¡¨, IEEE Microelectronic Test Structures Conference, pp. 95-98, Feb. 1999.
    [20] S. H. M. Jen, C.C. Enz, D. R.Pehlke, et al. ¡§Accurate modeling and parameter extraction for MOS transistors valid up to 10 GHz¡¨, IEEE Trans. on Electron Devices, vol. 46, no. 11, pp.2217-2226, Nov. 1999.
    [21] G. Dambrine, A. Cappy, F. Heliodore and E. Playez, ¡§ A new method for determining the FET small-signal equivalent circuit¡¨, IEEE Trans. on Microwave Theory and Techniques, vol. 36, pp. 1151-1159, July 1988.
    [22] T. Manku, M. Obrecht and Y. Lin, ¡§RF simulations and physics of the channel noise parameters within MOS transistors¡¨, in Proc. Custom Integrated Circuits Conference (CICC), pp. 369-372, 1999.
    [23] F. M. Klaasen, ¡§High frequency noise of the function field-effect transistor¡¨, IEEE Trans. on Electron Devices, vol. 14, no. 7, pp.368-373, 1967.
    [24] A. Cappy, A. Vanoverschelde, M. schortgen and G. Salmer, ¡§Noise modeling in submicrometer-gate two dimensional electron-gas field effect transistor¡¨, IEEE Trans. on Electron Devices, vol. 32, no. 11, pp. 2787-2795, 1985.
    [25] A. A. Abidi, ¡§High frequency noise measurements on FETs with small dimensions¡¨, IEEE Trans. on Electron Devices, vol. 33, no. 11, pp. 1801-1805, Nov. 1986. 
    [26] A. J. Scholten, L. F. Tiemeijer, R. V. Langevelde, et al. ¡§Noise Modeling for RF CMOS circuit simulation¡¨, IEEE Trans. on Electron Devices, vol. 50, no. 3, pp. 618-632, Mar. 2003.
    [27] B. Wang, J. R. Hellums and C. G. Sodini, ¡§MOSFET thermal noise modeling for analog integrated circuits¡¨, IEEE Journal of Solid-State Circuits, vol. 29, no. 7, pp. 833-835, July 1994.
    [28] G. Dambrine, J. P. Raskin, F. Danneville, et al. ¡§High frequency four noise parameters of silicon-on-indulator-based technology MOSFET for the design of low-noise RF integrated circuits¡¨, IEEE Trans. on Electron Devices, vol. 46, no. 8, pp.1733-1741, Aug. 1999.
    [29] S. Tedja, J. V. D. Spiegel and H. H. Williams, ¡§Analytical and experimental studies of thermal noise in MOSFET¡¦s¡¨, IEEE Trans. on Electron Devices, vol. 41, pp. 2069-2075, Nov. 1994.
    [30] A. Cappy, ¡§Noise modeling and measurement techniques¡¨, IEEE Trans. on Microwave Theory and Techniques, vol. 36, no. 1, pp. 1-10, Jan. 1998.
    [31] A. Cappy, W. Heinrich, ¡§High frequency FET noise performance: a new approach¡¨, IEEE Trans. on Electron Devices, vol. 36, no. 2, pp.403-409, Feb 1989.
    [32] J. J. Ou, X. Jin, C. Hu and P. R. Gray, ¡§ Submicron CMOS thermal noise modeling from an RF perspective¡¨, in Technical Digest of VLSI Technology, pp. 151-152, 1999.
    [33] D. K. Shaeffer and T. H. Lee, ¡§A 1.5 V 1.5 GHz CMOS low noise amplifier¡¨, IEEE Journal of Solid-State Circuit, vol. 31, no. 5, pp. 745-759, May. 1997. 
    [34] T. H. Lee, The design of CMOS radio frequency integrated circuits, Combridge, 1998.
    [35] B. Razavi, RF microelectronics, Prentice Hall Inc, New York, 1998.
    [36] S. W. Yoon, E. C. Park, C. H. Lee, S. Sim, S. G. Lee, E. Yoon, J. Laskar and S. Hong, ¡§Cross-coupled differential oscillator MMICs with low phase-noise performance¡¨, IEEE Microwave and Wireless Components Letters, Vol. 11, Dec. 2001, pp. 495¡V497.
    [37] P. Andreani and H. Sjoland, ¡§A 1.8 GHz CMOS VCO with reduced phase noise¡¨, in Tech. Digest of VLSI Circuits, pp. 121-122, 2001.
    [38] F. Herzel, H. Erzgraber and P. Weger, ¡§Integrated CMOS wideband oscillator for RF applications¡¨, IEE Electronics Letters, Vol. 37, pp. 330¡V331, Mar. 2001.
    [39] A. Dec and K. Suyama, ¡§A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors¡¨, IEEE Journal of Solid-State Circuits, Vol. 35, pp. 1231-1237, Aug. 2000.
    [40] E. Cijvat, ¡§A 0.35 mm CMOS DCS front-end with fully integrated VCO¡¨, in Tech. Digest of IEEE International Conference on Electronics, Circuits and Systems, Vol.3, pp. 1595-1598, 2001.
    [41] R. Bunch and S. Raman, ¡§A 0.35 mm CMOS 2.5 GHz complementary -GM VCO using PMOS inversion mode varactors¡¨, in Digest of IEEE RFIC Symposium, pp. 49-52, 2001.
    [42] S. Yang, R. Mason and C. Plett, ¡§CMOS LNA in wireless applications¡¨, in Proc. of IEEE Vehicula Technology Conference, vol. 3, pp. 1920-1924, May 1999.
    [43] X. Li, H. Kim, M. Ismail and H. Olsson, ¡§A novel design approach for GHz CMOS low noise amplifier¡¨, in Technical. Digest of Radio and Wireless Conference (RAWCON), pp. 285-288, Aug. 1999.
    [44] W. Guo and D. Huang, ¡§Noise and linearity analysis for a 1.9 GHz CMOS LNA¡¨, IEEE symposium on Circuit and Systems, vol. 2, pp. 409-414, Oct. 2002.
    [45] H. Samavati, H. R. Rategh and T. H. Lee, ¡§A 5 GHz CMOS wireless Lan receiver front end¡¨, IEEE Journal of Solid-State Circuits, vol. 35, pp. 765-772, May 2000.
    [46] W. Hu, Y. Guo, Z. Qiu and L. Yang, ¡§A 1.2 V 2.4 GHz 0.18 mm CMOS low noise amplifier¡¨, in proceeding of IEEE Circuits and Systems Conference, vol. 1, pp. 470-473, July 2002.
    [47] J. Hauptmann, F. Dielacher, R. Steiner, C. C. Enz and F. Krummenacher, ¡§A low noise amplifier with automatic gain control and anticlipping control in CMOS technology¡¨, IEEE Journal of Solid-State Circuits, vol. 27, pp. 974-981, July 1992.
    [48] C. Y. Cha and S. G. Lee, ¡§A low power, high gain LNA topology¡¨, in proceeding of IEEE Microwave and Millimeter Wave Technology, pp. 420-423, Sep. 2000.
    [49] H. Fouad, K. Sharaf, E. E. Diwany and H. E. Hennawy, ¡§An RF CMOS caacode LNA with current reuse and inductive source degeneration¡¨, IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 14-17, Aug. 2001.
    [50] D. K. Shaeffer and T. H. Lee ¡§A 1.5 V, 1.5 GHz CMOS low noise amplifier¡¨, IEEE Journal of. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
    [51] P. Andreani and H. Sjoland, ¡§Noise optimization of an inductively degenerated CMOS low noise amplifier¡¨, IEEE Trans. on Circuits and Systems, vol. 48, pp. 835-841, Set. 2001.
    [52] J. Harvey and R. Harjani, ¡§Analysis and design of an integrated quadrature mixer with improve noise, gain and image rejection¡¨, IEEE Symposium on Circuits and Systems, vol. 4, pp. 786-789, May 2001.
    [53] R. F. Salem, S. H. Galal, M. S. Tawfik and H. F. Ragaie, ¡§A new highly linear CMOS mixer suitable for deep submicron technologies¡¨, IEEE Conference on Circuits and Systems, vol. 1, pp. 81-84, Sep. 2002.
    [54] P. J. Sulivan, B. A. Xavier and W. H. Ku, ¡§Low voltage performance of a microwave CMOS Gilbert cell mixer¡¨, IEEE Journal of Solid-State Circuits, vol. 32, pp. 1151-1155, May 1997.
    [55] H. M. Wang, ¡§ A 1 V multigigahertz RF mixer core in 0.5 mm CMOS¡¨, IEEE Journal of Solid-State Circuit, vol. 33, no. 12, pp. 2265-2267, Dec. 1998.
    [56] B. Gilbert, ¡§A precise four quadrant multipier with subnanosecond response¡¨, IEEE Journal of Solid-State Circuits, vol. SC-3, pp. 365-373, Dec. 1968.
    [57] S. J. Jou, S. Y. Wu and C. K. Wang, ¡§Low power multirate architecture IF digital frequency down converter¡¨, IEEE Trans. on Circuits and Systems, vol. 45, pp. 1487-1494, 1998.
    [58] W. Sheng, B. Xia, A. E. Emira, X. Chunyu, S. T. Moon and E. S. Sinenicio, ¡§A 3 V 0.35 mm CMOS bluetooth receiver IC¡¨, IEEE Journal of Solid-State Circuits, vol. 38, pp. 30-42, Jan. 2003.
    [59] T. Sandstrom and L. Sundstrom, ¡§ A 1.8 GHz double-balanced CMOS receiver front-end¡¨, IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp. 834-837, Aug. 1999.
    [60] B. Razavi, ¡§CMOS RF receiver designs for wireless LAN applications¡¨, in Technical Digest of Radio and Wireless Conference (RAWCON), pp. 275-280, Aug. 1999.
    [61] S. Mahdavi and A. A. Abidi, ¡§Fully integrated 2.2 mW CMOS front-end for a 900 MHz zero IF wireless receiver¡¨, in Technical Digest of VLSI Circuits, pp. 251-252, Jun. 2001.
    [62] B. Razavi. ¡§A 5.2 GHz CMOS receiver with 62 dB image rejection¡¨, IEEE Journal of Solid-State Circuits, vol. 36, pp. 810-815, May 2001.
    [63] A.A. Ketterson, J. W. Seo, M. H. Tong, K. L. Nummlia, J. J. Morikuni, K. Y. Cheng, S. M. Kang, and I. Adesida, ¡§A MODFET-based optoelectronic integrated circuit receiver for optical interconnects¡¨, IEEE Trans. on Electron Devices, vol. 40, pp. 1406-1416, 1993
    [64] Y. Zebda, R. Lai, P. Bhattacharya, D. Pavlidis, P. R. Berger, and T. L. Brock, ¡§Monolithically integrated InP-based front-end photoreceivers¡¨, IEEE Trans. on Electron Devices, vol. 38, pp. 1324-1333, 1991
    [65] B. Razavi ¡§Prospects of CMOS technology for high-speed optical communication circuit¡¨, IEEE Journal of Solid-State Circuit, vol. 37, pp. 1135-1145, Set. 2002.
    [66] T. Yoon, B. Jalali, ¡§1 Gbit/s fiber channel CMOS transimpedance amplifier¡¨, IEE Electronics Letters, vol. 33, pp. 588-589, 1997
    [67] C. Toumazou, S.M. Park, ¡§Wideband low noise CMOS transimpedance amplifier for gigahertz operation¡¨, IEE Electronics Letters, vol. 32, pp. 1194-1196, 1996
    [68] S.M. Park, C. Toumazou, ¡§Gigahertz low noise CMOS transimpedance amplifier¡¨, IEEE International Symposium on Circuit and Systems, pp. 209-212, 1997
    [69] H. Kikuchi, Y. Miyagawa, and T. Kimura, ¡§Broad-band GaAs monolithic equalizing amplifier for multigigabit-per-second optical receivers¡¨, IEEE Trans. Microwave Theory Tech., vol. 38, pp. 1916-1923, 1990.
    [70] F.T. Chien, Y.J. Chan ¡§Bandwidth enhancement of transimpedance amplifier by a capacitive-peaking design¡¨, IEEE Journal of Solid-State Circuit, vol. 34 , pp. 1167-1170, 1999
    [71] N. Ohkawa, ¡§Fiber-optic multigigabit GaAs MIC front-end circuit with inductor peaking¡¨, J. Lightwave Technol, vol. 6, pp. 1665-1675,1988.
    [72] J. J. Morikuni, S. M. Kang, ¡§ An analysis of inductive peaking in high frequency amplifiers¡¨, IEEE symposium on Circuit and Systems, vol. 6, pp. 2848-2851, May 1992.
    [73] M. Kossel, C. Menolfi, T. Morf, M Schmatz and T. Toifl, ¡§ Wideband CMOS transimpedance amplifier¡¨, Electronic Letters, vol. 39, no. 3, pp. 587-588, Apr. 2003.
    [74] J. J. Morikuni, S. M. Kang, ¡§ An analysis of inductive peaking in photoreceiver design¡¨, Journal of Lightwave Technol, vol. 10, pp. 1426-1437, Oct. 1992.
    [75] T. Yoon and B. Jalali, ¡§ Front-end CMOS chipset for fiber-based gigabit Ethernet¡¨, in Technical Digest of VLSI Technology, pp. 188-191, June 1998.
    [76] C.W. Kuo, C.C. Hsiao, C.C. Ho, and Y.J. Chan, ¡§Scalable large-signal model of 0.18 mm CMOS process for rf power predictions¡¨, Solid-State Electronics, vol 47, pp.77-81, 2002.
    [77] H.-M. Rein, R. Schmid, P. Weger, T. Smith, T. Herzog, and R. Lachner, ¡§A versatile Si-Bipolar Driver Circuit with high output voltage swing for external and direct laser modulation in 10 Gb/s optical-fiber links¡¨, IEEE Journal of Solid-State Circuits, vol. 29, pp. 1014-1021, 1994.
    [78] P. C. Huang, Y. H. Chen and C. K. Wang, ¡§ A 2 V 10.7 MHz CMOS limiting amplifier/RSSI¡¨, IEEE Journal of Solid-State Circuit, vol. 35, no. 10, pp. 1474-1480, Oct. 2000.
    [79] R. Castello and H. Rein, ¡§ Bipolar high gain limiting amplifier IC for optical fiber receivers operating up to 4 Gb/s¡¨, IEEE Trans. on Circuit and Systems, vol. 42 , pp. 827-840, Nov 1995.
    [80] E. Sackinger and E. Fischer, ¡§ A 3 GHz, 32 dB CMOS limiting amplifier for SONET OC-48 receivers¡¨, in Tech. Digest of IEEE international Conference on Solid-State Circuits, pp. 158-159, Feb. 2000.
    [81] T. Yoon and B. Jalali, ¡§622Mbit/s CMOS limiting amplifier with 40 dB dynamic range¡¨, IEE Electronic Letters, vol. 32, pp. 1920-1922, Sep. 1996.
    [82] R. Tao, Z. G. Wang, T. T. Xie, H. T. Chen, Y. Dong and S. Z. Xie, ¡§ CMOS limiting amplifier for SDH STM-16 optical receiver¡¨, IEE Electronic Letters, vol. 37, pp. 236-237, Feb. 2001.
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