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Student Number 87324022 Author Chin-Wei Kuo(³¢®ÊÞ³) Author's Email Address cwkuo@ee.ncu.edu.tw Statistics This thesis had been viewed 3468 times. Download 2050 times. Department Electrical Engineering Year 2003 Semester 1 Degree Ph.D. Type of Document Doctoral Dissertation Language English Title The large-signal model of complementary MOSFETs and its applications in high speed communication circuits Date of Defense 2003-09-26 Page Count 120 Keyword large-signal model MOSFET power contour Abstract In near decades, the rapid growth of optical and wireless communication systems market drive optical and radio frequency integrated circuits into a higher level integration with lower power consumption. To achieve these goals, the designers have to integrate the discrete circuits on the same substrate to reduce the size and the cost. However, with the scaling down of the CMOS channel length into deep sub-micrometer scale, the characteristic of CMOS device could be improved for GHz application.

In the chapter 2, this thesis survey the modified MOSFET RF large-signal model in 0.18 mm CMOS technologies for optical and the RF circuits design. The modified large-signal model consists of a conventional BSM3v3 model and the passive networks which represent the parasistic effects of the MOSFET.

In the chapter 3, this study proposed a self-define large-signal model for 50 mm-wide nMOS transistor. The self-defined model can predict not only dc and microwave performance well but also in noise characteristics by using P, R, C noise parameters calculation. In this empirical model, all the parameters were extracted from measurement results; moreover, the intrinsic parameters could be characterized as functions of the gate to source voltage (Vgsi) and drain to source voltage (Vdsi).

Moreover, in the chapter 4, various RF circuits are presented based on the modified RF large-signal model described in the chapter 2. The RF circuits include a 2.4 GHz voltage-controlled oscillator, a 2.4 GHz low-noise amplifier, a double-balanced mixer and a 2.4 GHz down-converter. Most of the circuits use the MOSFET RF large-signal model described in the chapter 2. The voltage-controlled oscillator delivered ¡V5 dBm to 4 dBm as the oscillated frequency moved from 2.34 GHz to 2.45 GHz, which resulted in a tuning factor of 183 MHz/V. Furthermore, the phase noise of the VCO is ¡V110 dBc/Hz with a 1MHz offset at 2.4 GHz operation. Besides, the 2.4 GHz low-noise amplifier with common-source inductive degeneration architecture was presented. The LNA has the power gain of 14 dB at 2.4 GHz with a Fmin of 2.1 dB; as to the linearity behaviors, the P1dB and and the IIP3 of the LNA are ¡V4 dBm and 0 dBm, respectively. Moreover, the double-balance Gilbert cell mixer was introduce for the down-conversion application, the mixer provide the conversion of 3 dB with a P1dB of ¡V5 dBm; the RF-to-IF isolations are all greater than 18 dB and the LO-to-IF isolation can achieve 33 dB. As to the consideration of linearity, the IP3 of the mixer is located at input power of 0 dBm. At the last, a 2.4 GHz down-converter was proposed, which converts the 2.45 GHz RF signal to 80 MHz IF signal with the conversion of 12 dB and consuming 80 mW of DC power. Also, the P1dB and IIP3 of the CMOS down-converter is ¡V12 dBm and ¡V2 dBm.

In the chapter 5, the optical transimpedance amplifiers and one stage limiting amplifier were presented. Here we used two peaking mechanisms for the TIA design namely, capacitive peaking and inductive peaking. In the TIAs design with the capacitive peaking approach, the 3 dB bandwidth can be enhanced from 875 MHz to 1.35 GHz without sacrificing its low-frequency gain. As to the inductive peaking design, both gate-inductive peaking and drain inductive peaking were presented in this chapter. By using the gate and drain inductive peaking approach, the 3-dB bandwidth could be improved from 4.4 GHz to 6.8 GHz and from 4.4 GHz to 6.8 GHz, however, the drain-inductive peaking demonstrated the superior characteristics in the output eye patterns. On the part of limiting amplifier, a one stage LA for 7 Gbps application was fabricated and characterized with the fully differential topology, which has the power gain of 13.8 dB and the 3 dB bandwidth can up to 4.4 GHz.Table of Content TABLE OF CONTENTS

Abstract I

Figure captions VIII

Table captions XIII

Chapter 1 Introductions

1-1. Motivation 1

1-2. Thesis Organization 2

Chapter 2 The Modified MOSFET Scaleable RF Large-Signal Model

2-1. Introduction 4

2-2. MOSFET Device Layout 5

2-3. Scaleable RF Large-Signal Model for 0.18-mm MOSFETs 8

2-4. Passive Component Models 22

2-4-1. The equivalent circuit model of spiral inductors 22

2-4-2. The equivalent circuit model of MIM capacitors 26

2-5. Summary 28

Chapter 3 The Self-Defined Empirical MOSFER RF Large-Signal Model

3-1. Introduction 29

3-2. MOSFET Large-Signal Model and Parameter Extraction 30

3-2-1 The extractions of the DC-related parameters and I-V prediction 31

3-2-2 The extractions of the extrinsic components 33

3-2-3 The microwave and power performance prediction 35

3-3. The prediction of noise performance 39

3-3-1 Parameters of the thermal noise 39

3-3-2 High frequency noise model of nMOSFET 41

3-4. The design of Low noise amplifier with different models 42

3-5. Summary 46

Chapter 4 CMOS RF Circuits Design

4-1.Introduction 47

4-2. The Microwave Voltage-Controlled Oscillators 49

4-2-1 Basic concept of the cross-coupled oscillator 49

4-2-2 The 2.4 GHz Monolithic CMOS voltage-controlled oscillator 52

4-3. The Microwave Low-Noise Amplifier 56

4-3-1 Basic concept of the LNA 56

4-3-2 Topologies of the LNA 57

4-3-3 The 2.4 GHz low-noise amplifier design 61

4-4. The Microwave Gilbert-Cell Mixer 62

4-4-1 Basic concept of the Gilbert-cell mixer 66

4-4-2 The Monolithic CMOS double-balanced Gilbert-cell Mixer 67

4-5. The Microwave Down-Converter 72

4-5-1 The architecture of the 2.4 GHz CMOS down-converter 72

4-5-2 The architecture of the 2.4 GHz CMOS down-converter 72

4-6. Summary 77

Chapter 5 CMOS Integrated Circuits for Optical Communications

5-1. Introduction 78

5-2. The Design of Transimpedance Amplifier 79

5-2-1 The TIA design with the capacitive peaking mechanism 80

5-2-2 The TIA design with the inductive peaking mechanism 86

5-3. The Design of limiting Amplifier 102

5-3-1 The technique of broadband design in limiting amplifier 102

5-3-2 The design of the limiting amplifier 104

5-3-3 The experimental results 105

5-4. Summary 108

Chapter 6 Conclusions 109

Bibliongraphy 111

Publication List 118Reference Bibliography

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