Title page for 87324006


[Back to Results | New Search]

Student Number 87324006
Author Shu-Hua Kuo(Q)
Author's Email Address No Public.
Statistics This thesis had been viewed 2525 times. Download 1855 times.
Department Electrical Engineering
Year 1999
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title The Low Noise Output Buffer Design Techniques and Transceiver Implementation for USB2 Physical Layer
Date of Defense 2000-06-12
Page Count 115
Keyword
  • Ground bounce
  • SSN
  • SSO
  • USB
  • Abstract High-speed I/O is the key component to successfully transmit data between electronic devices. Simultaneous switching noise (SSN) or called ground bounce is one of the major noise sources in high-speed digital circuit. There are two research topics in this thesis. First we focus on the overview of SSN. We will propose an output buffer - AC/DC for reducing SSN, output signal ringing and maintain DC current capability. The test chip by using UMC 0.35um 1P5M digital process will be implemented to verify the theoretical analysis results and circuit design techniques. For example, SSO improvement from 3 to 11 for the YC2/ACDC2 cases, considering the Quiet VDD case. Measurement results show that our invention can reduce the output ringing by 60%, and VDD/GND line bounce by 40% when comparing with conventional buffers used in standard commercial cell library with 2ns rise/fall time and 40pF output loading capability. Also we propose a characterization procedure to estimate power pads for simultaneous switching outputs (SSO).
    The Universal Serial Bus (USB) technology is now becoming an integral part of the personal computer platform. USB is one of the first I/O ports where several types of devices can be connected simultaneously. Thus, in the second research topic, the transceiver architecture and circuit is proposed for USB2 high-speed mode with 480Mb/s bandwidth. The physical layer of USB2 consists of transceiver, two envelope detector, and clock recovery.
    Table of Content Contents
    AbstractKKKKKKKKKKKKKKKKKKKKKKKKKi
    AcknowledgementsKKKKKKKKKKKKKKKKKKKii
    ContentsKKKKKKKKKKKKKKKKKKKKKKKKiii
    List of FiguresKKKKKKKKKKKKKKKKKKKKKvii
    List of TablesKKKKKKKKKKKKKKKKKKKKKKKxi
    1 IntroductionKKKKKKKKKKKKKKKKKKKKKKKKKK...1
    1.1 MotivationKKKKKKKKKKKKKKKKKKKKKKKKK.1
    1.2 Thesis OrganizationKKKKKKKKKKKKKKKKKKKKK.3
    2 Low Noise Output Buffer Design TechniquesKKKKKKKKKKK...4
    2.1 IntroductionKKKKKKKKKKKKKKKKKKKKKKK..K.4
    2.2 The Analysis of Simultaneous Switching Noise and Simultaneous Switching OutputsK5
    2.3 Summary of SSN reduction guidelineKKKKKKKKKKKKK10
    2.4 Overview of Simultaneous Switching Noise Reduction Techniques..11
    2.4.1 Weighted and Distributed MethodKKKKKKKKKKK11
    2.4.2 Low Bouncing Output Driver MethodKKKKKKKKK12
    2.4.3 CMOS Output Buffer with Reduced L-di/dt NoiseKKKK13
    2.4.4 Ground Bounce Isolated Output BufferKKKKKKKKK15
    2.5 Proposed Low Noise Output Buffer Design TechniquesKKKKK16
    2.5.1 Design Techniques to reduce SSN and Output RingingKK17
    2.5.2 Basic OperationKKKKKKKKKKKKKKKKKKK18
    2.5.3 Simulation ResultsKKKKKKKKKKKKKKKKKK22
    2.6 SummaryKKKKKKKKKKKKKKKKKKKKKKKKK32
    3 Characterization of Simultaneous Switching OutputsKKKKKKK33
    3.1 IntroductionKKKKKKKKKKKKKKKKKKKKKKK....33
    3.1.1 SSO Classification and DefinitionKKKKKKKKKKK33
    3.1.2 Static and Dynamic SSN MarginKKKKKKKKKKKK35
    3.1.3 Simulation model for SSOKKKKKKKKKKKKKKK36
    3.2 Characterization of Simultaneous Switching OutputsKKKKKK38
    3.2.1 The Procedure of SSOP/SSOG EstimationKKKKKKKK38
    3.2.2 A Design Example of SSOG CharacterizationKKKKKKK40
    3.3 Characterization of TSSO (Excess Incremental Delay) KKKKKK42
    3.3.1 The Procedure of TSSO EstimationKKKKKKKKKKKK43
    3.3.2 A Design Example of TSSO CharacterizationKKKKKKK43
    4 Test Chip Implementation and Measurement ResultsKKKKKKK46
    4.1 Test Key for AC/DC Output BufferKKKKKKKKKKKKK46
    4.1.1 Testing ConsiderationKKKKKKKKKKKKKKKK47
    4.1.2 Layout ImplementationKKKKKKKKKKKKKKKK48
    4.2 Measurement ResultsKKKKKKKKKKKKKKKKKKKK51
    4.3 Chip SummaryKKKKKKKKKKKKKKKKKKKKKKK63
    5 Overview of USB2 SpecificationsKKKKKKKKKKKKKKKK65
    5.1 IntroductionKKKKKKKKKKKKKKKKKKKKKKKK65
    5.2 Architecture Overview of USB2K......................................................66
    5.2.1 USB2 System DescriptionKK..................................................66
    5.2.2 USB2 Physical InterfaceKK.........................................................67
    5.2.3 USB2 Data Flow Type....................................................................68
    5.2.4 USB2 Bus Protocol..........................................................................68
    5.3 Overview of USB2 Transceiver.................................................................69
    5.4 Specification of USB2 clock recovery.......................................................69
    5.5 Summary......................................................................................................71
    6 USB2 Transceiver ImplementationKKKKKKKKKKKKKKK72
    6.1 IntroductionKKKKKKKKKKKKKKKKKKKKKKKK72
    6.2 The Architecture of Transceiver for USB2KKKKKKKKKKK75
    6.3 The Circuit Design of TransmitterKKKKKKKKKKKKKKK76
    6.3.1 Parallel Input Serial Output CircuitKKKKKKKKKKK77
    6.3.2 Driver and Current SourceKKKKKKKKKKKKKKK79
    6.3.3 Voltage Reference CircuitKKKKKKKKKKKKKKK80
    6.3.4 Disconnection Envelop DetectorKKKKKKKKKKKK81
    6.4 The Circuit Design of ReceiverKKKKKKKKKKKKKKKK.83
    6.4.1 Level Shifter and Differential to Single CircuitKKKKKK85
    6.4.2 Transmission Envelop DetectorKKKKKKKKKKKKK86
    6.5 SummaryKKKKKKKKKKKKKKKKKKKKKKKKK88
    7 ConclusionsKKKKKKKKKKKKKKKKKKKKKKKKKK93
    BibliographyKKKKKKKKKKKKKKKKKKKKKKKKKKK94
    Reference Bibliography
    [1] R. Goyal, "Managing Signal Integrity," IEEE Spectrum, pp.54-58, Mar. 1994.
    [2] W. C. Cheng, "Simultaneous Switching Noise Analysis and Synthesizer for Low Bouncing Output Driver," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, Jun. 1998.
    [3] Y. T. Lin, "Investigation of Simultaneous Switching Noise for Signal Integrity in High Speed Digital Circuit Design," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, Jun. 1997.
    [4] H. C. Chow, "CMOS Output Buffer With Reduced Ldi/dt Noise," US Patent no. 5,708,386, Jan. 1998.
    [5] B. A. Sharpe-Geisler, S. Jose and Calif, "Groung Bounce Isolated Output Buffer," US Patent no. 5,438,277, Aug. 1995.
    [6] 0.35um Cell Library of Faraday Technology Corp. - YC24, 1998.
    [7] R. Senthinathan, J. L. Prince and S. Nimmagadda, "Effects of Skewing CMOS Output Driver Switching on the Simultaneous Switching Noise," 11th IEEE/CHMT International Electronics Manu. Tech. Symposium, pp.342-345, Sept. 1991.
    [8] LCB600K Cell-Based ASIC Products Design Manual, LSI Logic Corp., Nov. 1996.
    [9] "Simultaneous Switching Analysis Overview," ASIC Products Application Note of IBM, Aug. 1998.
    [10] Universal Serial Bus specification revision 2.0, Mar. 2000.
    [11] M. Horowitz, Chih-Kong Ken Yang and S. Sidiropoulos, "High-Speed Electrical Signaling: Overview and Limitations," IEEE Micro, vol.18, No.1, pp.12-24, Jan.-Feb. 1998.
    [12] USB Implementers Forum web page at http://www.usb.org.
    [13] Turi Aytur, Joe Gebits and Jason Golbus, "The Design of a High Speed Serial Link for IRAM," Berkeley University, cs254 Project Report, 12/8/1997. (http://iram.cs.berkeley.edu/serialio/cs254/)
    [14] R. D. Chiao, "The Low Noise Output Buffer Design Techniques and Clock Recovery Implementation for USB2 Physical Layer," M.S. dissertation, Dep. Elec. Eng., National Central University, Taiwan, May 1999.
    [15] S. J. Jou, W. C. Cheng and Y. T. Lin, "Simultaneous Switching Noise Analysis and Low Bouncing Buffer Design," IEEE Custom Integrated Circuits Conference, May 1998, pp.25.5.1-25.5.4.
    [16] Senthinathan, G. Tubbs and M. Schuelein, "Negative Feedback Influence on Simultaneous Switching CMOS Outputs," IEEE 1988 Custom Integrated Circuits Conference, pp.5.4.1-5.4.5, May 1998.
    [17] R. Vemuru, "Simultaneous Switching Noise Estimation for ASICs," IEEE International ASIC Conference and Exhibit 1995.
    [18] A. Vaidyanath, B. Thoroddsen and J. L. Prince, "Effects of CMOS Driver Loading Conditions on Simultaneous Switching Noise," IEEE Trans. Comp., Packaging, Manu., Technol.-Part B, vol.17, No.4, pp.480-485, Nov.1994.
    [19] R. Senthinathan and J. L. Prince, "Simultaneous Switching Ground Noise Calculation for Packaged CMOS Device," IEEE J. Solid-State Circuits, vol.26, No.11, pp.1724-1728, Nov. 1991.
    [20] Sakurai and A. R. Newton, "Alpha-Power Law NOSFET Model and its Applications to CMOS Inverter Delay and other Formulas," IEEE J. Solid-State Circuits, vol.25, No.2, pp.584-594, Apr. 1990.
    [21] R. Senthinathan and J. L. Prince, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise," IEEE J. Solid-State Circuits, vol.28, No.12, pp.1383-1388, Dec. 1993.
    Advisor
  • Shyh-Jye Jou(P@)
  • Files
  • 87324006.pdf
  • approve immediately
    Date of Submission 2000-06-12

    [Back to Results | New Search]


    Browse | Search All Available ETDs

    If you have dissertation-related questions, please contact with the NCU library extension service section.
    Our service phone is (03)422-7151 Ext. 57407,E-mail is also welcomed.