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Student Number 85324019
Author Gen-Hung Kuo(T)
Author's Email Address No Public.
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Department Electrical Engineering
Year 1997
Semester 2
Degree Master
Type of Document Master's Thesis
Language zh-TW.Big5 Chinese
Title VLSI Implementation of Timing recovery and Carrier Recovery for QAM/VSB Dual-mod CATV System
Date of Defense
Page Count 55
Keyword
  • Carrier Recovery
  • QAM
  • Timing Recovery
  • VSB
  • Abstract Abstract
    In the recent years, techniques for digital CATV modem,
    which can provide not only high quality video, but also many
    other functions such as entertainment, education, and computer
    transmission, had become a hot topic.In this thesis, a dual mode
    ( QAM and VSB ) transceiver architecture used in digital CATV
    will be introduced. A timing recovery which extracts timing
    informations from demodulated data, and a carrier recovery which
    extracts carrier informations are proposed to correctly
    demodulate the coming symbol.The proposed TR and CR use the MMSE
    algorithm, which can be used in both QAM and VSB signal, thus,
    the proposed TR and CR use almost the same hardware for the two
    mode. In the architecture design of TR and CR, algorithms used
    are modified so that the hardware complexity is dramatically
    reduced, while the performance about the sameFinally, the TR and
    CR are implemented by Compass 0.6 um High Density Standard Cell
    with TSMC 0.6um 1P3T process. The total gate is 12985 and the
    core size is . When operated in 2 V, the chip can operate in
    10.76 MHz, which fit the CATV specification and the power
    comsumption is estimated to be only 24.4mw
    Table of Content
    Reference
    Advisor
  • Jou Shyh-Jye(P@)
  • Files No Any Full Text File.
    Date of Submission

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