Title page for 85324017


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Student Number 85324017
Author Cheng-Shing Wu(dF)
Author's Email Address benior@ee.ncu.edu.tw
Statistics This thesis had been viewed 2174 times. Download 1141 times.
Department Electrical Engineering
Year 2001
Semester 2
Degree Ph.D.
Type of Document Doctoral Dissertation
Language English
Title A UNIFIED DESIGN FRAMEWORK OF HIGH-SPEED/LOW-COST ROTATION ENGINES:
AN ANGLE QUANTIZATION PERSPECTIVE
Date of Defense 2002-07-05
Page Count 123
Keyword
  • CORDIC
  • Vector Rotation
  • VLSI
  • Abstract Vector rotation is the key operation employed extensively in many digital
    signal processing (DSP) applications. In this dissertation, we introduce a new
    design concept called Angle Quantization (AQ). It can be used as a design
    index for vector rotational operation, where the rotational angle is known in
    advance. Based on the AQ process, we establish a unified design framework for
    cost-effective low-latency rotational algorithms and architectures. Several
    existing works, such as conventional CORDIC, AR-CORDIC, MVR-CORDIC, and
    EEAS-based CORDIC algorithm, can be fitted into the design framework, forming a
    Vector Rotational CORDIC Family. In addition, for MVR-CORDIC and
    EEAS-based CORDIC algorithm, we address their corresponding optimization
    searching algorithms, scaling operations, SQNR refinement schemes, systematic
    design flow, and VLSI architectures. All the statements are supported by
    extensive computer simulations and design examples. Based on the new design
    framework, we can realize high-speed/low-complexity rotational VLSI circuits,
    whereas without degrading the precision performance in fixed-point
    implementations.
    Table of Content Abstract  i
    Acknowledgement iii
    {1}Introduction}{1}
    {1.1}Digital Filters}{2}
    {1.2}Orthogonal Transformations}{6}
    {1.3}Research Focus and Contributions}{9}
    {1.3.1}Vector Rotation}{9}
    {1.3.2}Definition of Vector Rotation}{10}
    {1.3.3}Main Contributions}{11}
    {1.4}Thesis Organization}{14}
    {2}Angle Quantization Process and CORDIC Algorithm}{16}
    {2.1}Concept of Angle Quantization}{16}
    {2.1.1}Angle Quantization Process and SPT}{18}
    {2.2}Conventional CORDIC Algorithm}{19}
    {3}Modified Vector Rotational CORDIC Algorithm}{25}
    {3.1}The MVR-CORDIC Algorithm}{26}
    {3.2}Searching Algorithms and Comparisons}{29}
    {3.2.1}Searching Algorithms}{29}
    {3.2.2}Comparison of Computational Complexity and Error Performance}{32}
    {3.3}Relationship between Error Performance and Design Parameters}{35}
    {3.3.1}Error performance vs. number of elementary angles N}{36}
    {3.3.2}Error performance vs. restricted iteration number Rm}{37}
    {3.3.3}Error performance vs. searching block length D}{38}
    {3.4}Selective Pre-rotation Scheme}{38}
    {3.4.1}Conventional Pre-rotation Scheme}{38}
    {3.4.2}Selective Pre-rotation Scheme}{40}
    {3.4.3}Design Example and Simulation}{40}
    {3.5}Selective Scaling Scheme}{43}
    {3.5.1}Conventional Scaling Operations}{43}
    {3.5.2}Selective Scaling Scheme}{45}
    {3.5.3}Design Example}{46}
    {3.6}Iteration-tradeoff Scheme and Design Flow}{47}
    {3.6.1}Iteration-tradeoff Scheme for Rm and Rs}{47}
    {3.6.2}Design Flow for the MVR-CORDIC Algorithm}{49}
    {3.6.3}Design Example}{51}
    {3.7}VLSI Implementation of MVR-CORDIC}{54}
    {3.7.1}Iterative MVR-CORDIC Structure}{54}
    {3.7.2}Parallel and Pipelined MVR-CORDIC Structure}{56}
    {4}Extended Elementary Angle Set-Based CORDIC Algorithm}{58}
    {4.1}Extended Elementary-Angle Set (EEAS)}{59}
    {4.2}Searching Algorithms of the EEAS Scheme}{63}
    {4.2.1}Greedy Algorithm}{64}
    {4.2.2}Trellis-based Searching (TBS) Algorithm}{64}
    {4.2.3}Error Bound of TBS Algorithm}{69}
    {4.2.4}Comparison of Computational Complexity}{71}
    {4.3}Performance Comparisons}{74}
    {4.3.1}EEAS Scheme vs. AR Technique {74}
    {4.3.2}Trellis-based Searching (TBS) Algorithm vs. Greedy Algorithm}{75}
    {4.3.3}Combination of EEAS Scheme and the TBS Algorithm}{77}
    {4.4}Scaling Phase of the EEAS Scheme}{78}
    {4.4.1}The Extended Type-II (ET-II) Scaling Operation}{78}
    {4.4.2}Simulations}{79}
    {4.5}Combination of Micro-rotation Phase and Scaling Phase}{80}
    {4.5.1}Design Example}{80}
    {4.5.2}Simulation of complete EEAS-based CORDIC Algorithm}{81}
    {4.6}VLSI Structures of the EEAS-based CORDIC Algorithm}{83}
    {5}Vector Rotational CORDIC Family}{87}
    {5.1}Link AQ Process with Conventional CORDIC algorithm}{87}
    {5.2}Link AQ Process with the AR Technique}{89}
    {5.3}Link AQ Process with MVR-CORDIC Algorithm}{91}
    {5.4}Link AQ Process with EEAS-based CORDIC Algorithm}{92}
    {5.5}Generalized EEAS Scheme}{93}
    {5.6}Family of Vector Rotational CORDIC Algorithm}{94}
    {6}Conclusions and Future Researches}{96}
    {A}Analysis of SQNR}{100}
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    Advisor
  • An-Yeu Wu(dwt)
  • Shyh-Jye Jou(P@)
  • Files
  • 85324017.pdf
  • approve immediately
    Date of Submission 2002-07-11

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