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Student Number 82345011
Author Muh-Tian Shiue(K)
Author's Email Address No Public.
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Department Electrical Engineering
Year 1997
Semester 2
Degree Ph.D.
Type of Document Doctoral Dissertation
Language zh-TW.Big5 Chinese
Title Transceiver VLSI Design for High Speed Local Access Modems
Date of Defense
Page Count 142
Keyword
  • AGC
  • Blind Equalizer
  • Carrier Recovery
  • QAM
  • Timing Recovery
  • VSB
  • Abstract In this thesis a low-IF/baseband transceiver VLSI architecture
    for high speed digital communication systems over constrained-
    bandwidth channels is presented. For the transmitter end, a
    multi-mode digital modulator is proposed to generated the QAM,
    CAP, and VSB modulated signals in a low-IF band. Besides, a
    dual-mode 64-QAM/8-VSB digital modulator for CATV modem is
    implemented in 0.8 um CMOS single-poly double-metal (SPDM)
    process. At the proposed receiverend, a bandwidth regulation
    technique is disclosed to achieve faster convergence in the
    initial state and stable gain in the steady state for the
    digital automatic gain control (DAGC) and symbol timing recovery
    (TR) subsystems. Inorder to demonstrate the attractive
    characteristics of bandwidth regulation technique, a digital
    gain control (DGC) chip is implemented in 0.8 um CMOS SPDM
    process which can automatically regulate the loop bandwidth by a
    digital quantizer. Using commercial ADC and DAC components, the
    measured results shows that the realized dual-loop DAGC has
    1.1kHz bandwidth in the initial acquisition state, 100Hz
    bandwidth in the steady state, and less than 4ms settling time.
    Usually, the bandwidth-constrained channels induce harmful
    intersymbol interference (ISI). In order to overcome the harmful
    ISI, a quasi-fractionally spaced equalizer (quasi-FSE) structure
    is disclosed for the VSB system to achieve the superior
    performance and relax the load of timing recovery using complex
    symbol spaced input signals. Using the life data of digital TV
    program to update the digital equalizer coefficients, a multi-
    stage LMS-based blind equalization algorithm cooperating with
    the symbol timing and carrier recoveries well is proposed for
    higher order QAM, CAP, and VSB systems. Moreover, dual-mode
    blind fractionally spaced adaptive equalizer (BFSE) plus
    decision feedback equalizer (DFE), carrier recovery (CR), and
    timing recovery (TR) structures are proposed to construct a
    dual-mode QAM/VSB receiver for CATV modems using the proposed
    quasi-FSE structure and the proposed blind equalization
    algorithm. The circuit overhead including components and routing
    to achieve dual-mode 64-QAM/8-VSB blind equalizer is less than
    15% of aconventional QAM equalizer. Using the proposed multi-
    stage LMS-based blind equalization algorithm, finite word-length
    simulations of full system are conducted under the conditions of
    t/- 6kHz carrier frequency offset, +/-200ppm symbol-rate offset,
    -82dB carrier jetter at 20kHz away from the nominal carrier
    frequency, and 37dB SNR at ADC input. The simulation results
    show that the proposed VLSI architecture of dual-mode QAM/VSB
    receiver has more than 28dB SNR for the 8-VSB mode of cable
    modem. In contrast, there is more than 30dB SNR for the 64-QAM
    case.
    Table of Content Cover
    Contents
    List of Figures
    Chapter 1
    1.1 Background
    1.2 Motivation
    1.3 Contributions
    1.4 Thesis Organization
    Chapter 2
    2.1 Transmitter
    2.2 Receiver
    Chapter 3
    3.1 Introduction
    3.2 Quadrature Amplitude Modulation 39,39,40
    3.3 Carrierless AM-PM 10,12
    3.4 Vestigal Sidelband Modulation 41,42
    3.5 Proposed CAP-Based Phase Shift VSB Modulator 26,37
    3.6 VLSI Architecture for Multi-mode Digital Modulator 26,30
    3.7 VLSI Implementatuon for Dual-mode QAM/VSB Digital Modulator 30
    3.8 Summary
    Chapter 4
    4.1 Introdutction
    4.2 Signal Level Detection
    4.3 Proposed Dual-Loop Bandwidth Regulator
    4.4 VLSI Implementation of Dual-loop Digital Automatic Gain Control
    4.5 CMOS VLSI Circuit Implementations and Experiments
    4.6 Summary
    Chapter 5
    5.1 Introduction
    5.2 Adaptive Equalizer Structures
    5.3 Equalizer Adaptation Algorithms
    5.4 Simulation Results
    5.5 Summary
    Chapter 6
    6.1 Introduction
    6.2 Carrier Phase Extraction Schemes
    6.3 Carrier Recovery Architectures
    6.4 Dual-mode QAM/VSB Carrier Recovery
    6.5 Chip Implemantaion 30
    6.6 Summary
    Chapter 7
    7.1 Introduction
    7.2 Timing Extraction Schemes
    7.3 VLST Architecture Desigans for Timing Recovery
    7.4 Simulation Results
    7.5 Digitally -Calibrated VCO in CMOS VLST Technology
    7.6 Summary
    Chapter 8
    8.1 Introduction
    8.2 IF/Basedand Digital Receiver for CAP-Based xDSL Systems
    8.3 Dual-mode QAM/VSB Low-IF/Basedband Receiver for Cable Modem
    8.4 summary
    Chapter 9 Conclusion
    Reference
    Advisor
  • Juang Yau-Tarng, Wang Chorng-Kuang(, L)
  • Files No Any Full Text File.
    Date of Submission

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