碩博士論文 93521020 詳細資訊


[回到前頁查詢結果 | 重新搜尋]

姓名 黃瑜真(YU-JEN HUANG)
查詢紙本館藏  紙本論文權限2015-06-01開放
電子郵件信箱 93521020@cc.ncu.edu.tw
畢業系所 電機工程研究所(Electrical Engineering)
畢業學位 博士(Ph.D.) 畢業時期 100學年第2學期
論文名稱(中) 用於多核心/裸晶系統晶片之有效測試與良率提升技術
論文名稱(英) Efficient Test and Yield-Enhancement Techniques for Multi-Core/Die System Chips
檔案
93521020.pdf
  1. 本電子論文使用權限為三年後開放。
  2. 已達開放權限電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。
  3. 請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 三年後開放
論文語文/頁數 英文/209
統計 本論文已被瀏覽 818 次,被下載 5 次
摘要(中) 使用矽穿孔(through-silicon-via, TSV)作為垂直連接多層二維裸晶的三維技術是目前新興的積體電路設計技術之一。此技術可帶來許多優於二維積體電路設計技術的優點。然而,此技術目前存在許多挑戰,包含設計、製造、測試、良率等。這些挑戰在三維積體電路可量產前都須一一克服。其中,測試與良率為最關鍵的問題與挑戰。因此,對於三維晶片而言,有效的測試與良率提升技術是非常重要的。
三維晶片包含了數個二維晶片,其中二維晶片可能以多核心(multi-core)架構設計而成。無論是多核心裸晶或是多核心晶片,記憶體皆占了相當大的面積比例。因此在本論文第一部分,我們提出兩種測試多核心晶片中小記憶體的方法,稱為加強型IEEE 1500 測試封套(IEEE standard 1500 wrapper-based)測試方法及可擴充與低成本內建自我測試(scalable and low-cost built-in-self-test, BIST)電路方法。加強型IEEE 1500 測試封套測試技術利用既有的IEEE 1500 測試封套來測試已接到IEEE 1500 測試封套的記憶體。實驗結果顯示,此方法所付出的額外面積相當小,對於一個90nm 製程64K-bit 大小的單埠記憶體(single-port RAM)只需要0.58%,對於64K-bit 的多埠記憶體(multi-port RAMs)只要0.57%。用於記憶體陣列的可擴充與低成本內建自我測試電路可降低面積消耗與增加可擴充性,但不造成過長的測試時間。此外,我們提出錯誤定 位的方法來識別錯誤字組中錯誤位元的位置。實驗結果顯示,此方法對於16個64K-bit 的記憶體只需0.89%的額外面積消耗。我們亦實現此電路於測試晶片中,用來測試九個記憶體。
明顯地,在三維晶片中,矽穿孔的測試與良率相當重要。為了偵測與容忍錯誤的矽穿孔,我們在本論文的第二部分提出內建自我修復電路(built-in self-repair, BISR)來測試與修復三維晶片中的矽穿孔。此內建自我修復電路藉由矽穿孔排列成類似於記憶體的陣列形式,來提供較高的修復能力與良率。此外,我們亦提出廣域式(global)的修復資訊儲存方法來降低晶片中所需保險絲(fuse)的使用量。模擬與分析結果顯示出,與既有的矽穿孔修復架構以及達到相同的整體良率結果相比,所提出之內建自我修復電路可以大幅降低額外的面積消耗與測試時間。例如,對於有512 個矽穿孔的三維寬輸出入(wide-IO) DRAM,此內建自我修復技術可以降低32.4%的額外面積消耗與73.4%的測試時間。
論文的第三部分,我們討論了更複雜的矽穿孔錯誤模型(fault model) ─ 串音錯誤(crosstalk faults)。我們針對不同型態的矽穿孔串音錯誤提出不同的測試演算法。接著,我們提出內建自我測試電路與測試封套測試架構來實現測試演法。實驗結果顯示,對於一個32x16 大小的矽穿孔陣列與9T 串音錯誤模型,使用0.18μm製程實現的內建自我測試電路的額外面積消耗為28.1%。此矽穿孔的大小為15x15μm2。然而,對於整體面積為25mm2 的三維晶片而言,此額外面積消耗僅為1.86%。對於同樣的矽穿孔陣列,所提出的測試封套測試架構的額外面積消耗為60.6%。相較於一般需要兩個儲存元件的測試封套測試架構的額外面積消耗為73.92%而言,可節省18%的面積比例。
從應用面來看,堆疊記憶體的多核心裸晶已被視為相當適用於三維晶片中的架構。如上述提及,三維晶片的良率是關鍵的問題。因此,我們針對同質性(homogeneous)多核心記憶體與處理器堆疊的三維晶片,提出提升良率的方法,稱為一階層(one-level)與二階層式(two-level)的重組(reconfigurable)方法。在記憶體晶片中,我們增加了水平方向的位移重組方法。在處理器晶片中,我們增加了垂直方向的位移重組方法。因此,記憶體與處理器皆可位移來盡可能組成最多的好的記憶體與處理器組。同時,我們也提出啟發式演算法(heuristic algorithm)來快速的計算記憶體與處理器晶片的可重組性。因此,三維多核心晶片的良率就可藉由我們提出的方法來提升良率。實驗結果顯示,此重組方法僅使用可忽略的額外面積消耗即可明顯地提升整體良率。例如,對於容許錯一個記憶體與處理器組的64 核心的三維晶片而言,與沒有使用任何提升良率方法的晶圓對晶圓堆疊三維晶片相比,所提出的一階層與二階層方法可提升1.71%與6.08%的整體良。
摘要(英) Three-dimensional (3D) technology vertically integrating multiple 2D dies using the through-silicon-via (TSV) is one emerging integrated circuit design technology. It offers many advantages over the 2D integration technology. However, many challenges, such as the design, manufacturing, test, yield, and etc., should be overcome before the volume production of 3D ICs become possible. Among these challenges, test and yield are two key challenges. Effective test and yield-enhancement techniques are thus important for 3D ICs.
A 3D IC consists of multiple dies in which a die may be designed with multi-core architecture. Regardless of the multi-core die or the multi-die chip, memories usually dominate a large portion of the silicon area. In the first part of the thesis, therefore, we focus on the testing of RAMs in multi-core dies. Two low-area test schemes are proposed to test small RAMs, an enhanced IEEE 1500 wrapper-based test scheme and a scalable and low-cost built-in-self test (BIST) scheme. The enhanced IEEE 1500 wrapper-based test scheme utilizes existing IEEE standard 1500 wrappers to test RAMs connected to the IEEE 1500 wrappers. Experimental results show that the additional area cost for extending the IEEE 1500 wrapper to an enhanced one is small, which is only about 0.58% for a 64K-bit single-port RAM and only 0.57% for a 64K-bit two-port RAM in 90nm technology. The scalable and low-cost BIST scheme for an array of memories can reduce the area cost without incurring long testing time and increase the scalability. Furthermore, a fault-location approach is proposed to identify the positions of faulty bits in a faulty word. Simulation results show that the proposed BIST scheme has small area cost, e.g., the BIST circuit for 16 1024×64-bit RAMs only needs about 0.89%hardware overhead. A test chip is also implemented to demonstrate the proposed BIST scheme for 9 RAMs.
Clearly, the test and yield of TSV are very important for 3D ICs. To detect and tolerate defective TSVs, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3D ICs in the second part of the thesis. The BISR scheme, arranging the TSVs into arrays similar to memories, can provide high repair yield. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.
In the third part of the thesis, we discuss more complex fault models of TSVs — the crosstalk faults. Test algorithms for testing different types of crosstalk faults of TSVs are proposed. Then, a BIST architecture and the wrapper-based test architecture are proposed to realize the test algorithms for TSVs. Simulation results show that the area overhead of the proposed BIST circuit for a 32×16 TSV array with 9T crosstalk faults is 28.1% using 0.18μm CMOS technology, where each TSV cell size is 15 × 15μm2. However, the area overhead of the BIST circuit is only 1.86% to a 25mm2 die. The area overhead of the proposed wrapper-based test architecture is 60.6% for the same TSV array which can save 15% area overhead compared with the typical two-storage wrapper test architecture which has 73.92% area overhead to the TSV array.
In the application point of view, multi-core die stacked with memories has been considered as one good candidate for 3D ICs. As aforementioned, the yield is one critical issue for 3D ICs, therefore, we propose yield-enhancement techniques, one-level and two-level reconfiguration scheme, for homogeneous multi-core memory and processor stacked 3D ICs. For a memory and processor stacked 3D ICs, a horizontal shifting reconfiguration scheme is added in the memory die while a vertical shifting reconfiguration scheme is added in the processor die. Then memory and processor cores can be swapped which can make as many good memory-processor pairs as possible. Also, heuristic reconfiguration algorithms are developed to fast calculate the reconfigurability of the memory and processor dies. Then the yield of 3D multi-core ICs can be improved by the proposed yield enhancement techniques. Experimental results show that the proposed reconfiguration schemes can significantly increase the yield from 1% to 11% using negligible area overhead. For example, if the 3D IC is a 63-out-of-64 system, the proposed one-level and two-level reconfigurations schemes can increase 1.71% and 6.08% of final yield compared with randomly wafer-to-wafer stacking without any yield-enhancement technique.
關鍵字(中)
  • 三維晶片
  • 記憶體診斷
  • 記憶體測試
  • 良率提升
  • 系統晶片
  • 矽穿孔
  • 多核心
  • 內建自我測試
  • 內建自我修復
  • 隨機存取記憶體
  • 關鍵字(英)
  • 3D IC
  • through-silicon-via (TSV)
  • System-on-Chip (SOC)
  • random access memory (RAM)
  • multi-core
  • memory testing
  • diagnosis
  • built-in self-test
  • built-in self-repair
  • yield-enhancement
  • 論文目次 1 Introduction 1
    1.1 3D Integration Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
    1.1.1 TSV Techniques and Bonding Techniques . . . . . . . . . . . . . . . . . . 1
    1.1.2 3D IC Architectures and Applications . . . . . . . . . . . . . . . . . . . . 3
    1.1.3 Challenges of 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
    1.2 Test and Yield-Enhancement Techniques for 2D Dies . . . . . . . . . . . . . . . . 6
    1.2.1 2D System-on-Chips (SOCs) in a 3D IC . . . . . . . . . . . . . . . . . . . 6
    1.2.2 Memory Built-In Self-Test Circuit . . . . . . . . . . . . . . . . . . . . . . 8
    1.2.3 IEEE Standard 1500 Architecture . . . . . . . . . . . . . . . . . . . . . . 9
    1.2.4 Existing Memory Built-In Self-Test Schemes . . . . . . . . . . . . . . . . 10
    1.3 Test and Yield-Enhancement Techniques for 3D Dies . . . . . . . . . . . . . . . . 13
    1.3.1 Defects in TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
    1.3.2 Testing of 3D ICs and TSVs . . . . . . . . . . . . . . . . . . . . . . . . . 14
    1.3.3 Existing TSV Redundancy and Reconfiguration Schemes . . . . . . . . . . 16
    1.4 Thesis Scope and Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
    1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
    2 Built-In Self-Test Techniques for Small RAMs in SOCs 22
    2.1 Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . 23
    2.1.1 Architecture of the Enhanced IEEE 1500 Test Wrapper . . . . . . . . . . . 23
    2.1.2 Operations of the Proposed Enhanced 1500 Wrapper . . . . . . . . . . . . 25
    2.1.3 Implementation of Wrapper Cell and Address Generator . . . . . . . . . . 27
    2.1.4 Multi-Port RAM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
    2.1.5 Test Time Reduction Techniques . . . . . . . . . . . . . . . . . . . . . . . 31
    2.2 Pipelined BIST Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
    2.2.1 BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
    2.2.2 BIST Sharability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
    2.2.3 Test Time Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
    2.2.4 BIST for an Array of Memories . . . . . . . . . . . . . . . . . . . . . . . 42
    2.2.5 Support of Interconnection Test . . . . . . . . . . . . . . . . . . . . . . . 43
    2.3 Memory Repair and Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
    2.3.1 Memory Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
    2.3.2 Memory Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
    2.3.3 BIST Modification for Memory Diagnosis . . . . . . . . . . . . . . . . . . 49
    2.4 Simulation and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . 51
    2.4.1 Design of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 51
    2.4.2 Analysis of the Enhanced IEEE 1500 wrapper . . . . . . . . . . . . . . . . 53
    2.4.3 Design of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . . 59
    2.4.4 Analysis of the Pipelined BIST Circuit . . . . . . . . . . . . . . . . . . . 63
    2.4.5 Architecture of the Test Chip . . . . . . . . . . . . . . . . . . . . . . . . . 66
    2.4.6 Results of Wafer-level Test . . . . . . . . . . . . . . . . . . . . . . . . . . 66
    2.4.7 Results of Post-bond Test . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
    2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
    3 Self-Test and Repair for TSVs in 3D ICs 73
    3.1 Proposed Testing Scheme for TSV Arrays . . . . . . . . . . . . . . . . . . . . . . 74
    3.1.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
    3.1.2 Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
    3.1.3 KGS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
    3.2 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
    3.2.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 81
    3.2.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
    3.2.3 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
    3.3 Proposed TSV Redundancy and Reconfiguration Scheme . . . . . . . . . . . . . . 87
    3.4 Proposed BISR Scheme for TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 92
    3.4.1 Overview of the BISR scheme . . . . . . . . . . . . . . . . . . . . . . . . 92
    3.4.2 BISR Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
    3.4.3 BISR Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
    3.5 Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
    3.5.1 Connection of Repair Register and Fuse . . . . . . . . . . . . . . . . . . . 99
    3.5.2 Design of Fuse Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103
    3.6 Analysis and Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . 104
    3.6.1 Hardware Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
    3.6.2 Fuse Cost Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
    3.6.3 Yield Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
    3.6.4 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
    3.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
    4 Testing Crosstalk Faults of TSVs in 3D ICs 116
    4.1 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
    4.1.1 5-TSV and 9-TSV Fault Models . . . . . . . . . . . . . . . . . . . . . . . 118
    4.1.2 Coupling Effects of TSVs . . . . . . . . . . . . . . . . . . . . . . . . . . 119
    4.2 Proposed Test Algorithms for Crosstalk Faults of TSVs . . . . . . . . . . . . . . . 121
    4.2.1 Parallel Test Algorithms and Wrapper-based Test Scheme . . . . . . . . . 121
    4.2.2 Test Algorithms for 5T-XF using BIST Scheme . . . . . . . . . . . . . . . 125
    4.2.3 Test Algorithms for 9T-XF using BIST Scheme . . . . . . . . . . . . . . . 126
    4.3 Proposed Testing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
    4.3.1 Proposed BIST Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 129
    4.3.2 Test Operation Flow of the BIST Scheme . . . . . . . . . . . . . . . . . . 132
    4.4 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
    4.4.1 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 133
    4.4.2 Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
    4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
    5 Yield-Enhancement Techniques for Memory and Processor Stacked 3D ICs 141
    5.1 Yield of Multi-Core 2D and 3D ICs . . . . . . . . . . . . . . . . . . . . . . . . . 142
    5.2 Yield-Enhancement Techniques for 3D ICs . . . . . . . . . . . . . . . . . . . . . 143
    5.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
    5.4 Proposed Yield Enhancement Techniques . . . . . . . . . . . . . . . . . . . . . . 145
    5.4.1 Proposed Yield-Enhancement Flow . . . . . . . . . . . . . . . . . . . . . 145
    5.4.2 Proposed One-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 146
    5.4.3 Proposed Two-level Reconfiguration Scheme . . . . . . . . . . . . . . . . 153
    5.4.4 Wafer Matching Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
    5.5 Simulation Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
    5.5.1 Area Overhead and Yield Model . . . . . . . . . . . . . . . . . . . . . . . 159
    5.5.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
    5.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
    6 Conclusion and Future Work 169
    6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
    6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
    參考文獻 [1] A.-C. Hsieh and T.-T. Hwang, “TSV redundancy: architecture and design issues in 3-D IC,” IEEE Trans. on VLSI Systems, vol. 20, no. 4, pp. 711–722, Apr. 2012.
    [2] D.-M. Kwai and C.-T. Lin, “3D stacked IC layout considering bond pad density and doubling for manufacturing yield improvement,” in Proc. 12th Int’l Symp. on Quality Electronic Design (ISQED), Mar. 2011, pp. 1–6.
    [3] E. J. Marinissen and Y. Zorian, “Testing 3D chips containing through-silicon vias,” in Proc. Int’l Test Conf. (ITC), Nov. 2009, ET1.1, pp. 1–11.
    [4] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST compiler for embedded memories,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299–307.
    [5] IEEE, “IEEE 1500 standard for embedded core test (SECT),” http://grouper.ieee.org/groups/1500/, 2005.
    [6] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, “Automatic generation of memory built-in self-test cores for system-on-chip,” in Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 91–96.
    [7] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal, “A serial interfacing technique for external and built-in self-testing of embedded memories,” IEEE Design & Test of Computers, vol. 7, no. 2, pp. 56–64, Apr. 1990.
    [8] B. Wang, Y. Wu, and A. Ivanov, “A fast diagnosis scheme for distributed small embedded SRAMs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2005, pp. 852–857.
    [9] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tehnunen, and L.-R. Zheng, “Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits,” in IEEE Int’l Conf. on 3D System Integration (3DIC), Sept. 2009, pp. 1–8.
    [10] I. Loi, F. Angiolini, S. Fujita, S. Mitra, and L. Benini, “Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 124–134, Jan. 2011.
    [11] U. Kang and et al., “8Gb 3-D DDR3 DRAM using through-silicon-via technology,” IEEE Jour. of Solid-State Circuits, vol. 45, no. 1, pp. 111–119, Jan. 2010.
    [12] M. Laisne, K. Arabi, and T. Petrov, “Systems and methods utilizing redundancy in semiconductor chip interconnects,” US Patent No. 20100060310 A1, Mar. 2010.
    [13] G. V. der Plas and et al., “Design issues and considerations for low-cost 3-D TSV IC technology,” IEEE Jour. of Solid-State Circuits, vol. 46, no. 1, pp. 293–307, Jan. 2011.
    [14] W.-L.Wang and K.-J. Lee, “A complete memory address generator for scan based march algorithm,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2005, pp. 83–88.
    [15] J. Cho and et al., “Modeling and analysis of through-silicon via (TSV) noise coupling and suppression using a guard ring,” IEEE Trans. on Components, Packaging, and Manufacturing Technology, vol. 1, no. 2, pp. 220–233, Feb. 2011.
    [16] C. Liu, T. Song, J. Cho, J. Kim, J. Kim, and S. K. Lim, “Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June 2011, pp. 783–788.
    [17] M. H. Tehranipour, N. Ahmed, and M. Nourani, “Testing SOC interconnects for signal integrity using extended JTAG architecture,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 5, pp. 800–811, May 2004.
    [18] V. F. Pavlidis and E. G. Friedman, “Interconnect-based design methodologies for three-dimensional integrated circuits,” Proceedings of the IEEE, vol. 97, no. 1, pp. 123–140, Jan. 2009.
    [19] M. Koyanagi, T. Fukushima, and T. Tanaka, “High-density through silicon vias for 3-D LSIs,” Proceedings of the IEEE, vol. 97, no. 1, pp. 49–59, Jan. 2009.
    [20] T. Zhang, R. Micheloni, G. Zhang, Z. R. Huang, and J. J.-Q. Lu, “3-D data storage, power delivery, and RF/optical transceiver–case studies of 3-D integration from system design perspectives,” Proceedings of the IEEE, vol. 97, no. 1, pp. 161–174, Jan. 2009.
    [21] J.-Q. Lu, “3-D hyperintegration and packaging technologies for micronano systems,” Proceedings of the IEEE, vol. 97, no. 1, pp. 18–30, Jan. 2009.
    [22] D. Wang, Y. Xie, Y. Hu, H. Li, and X. Li, “Hierarchical fault tolerance memory architecture with 3-dimensional interconnect,” in Proc. IEEE Region 10 Conference – TENCON, Oct. 2007, pp. 1–4.
    [23] S. Reda, G. Smith, and L. Smith, “Maximizing the functional yield of wafer-to-wafer 3-D integration,”
    IEEE Trans. on VLSI Systems, vol. 17, no. 9, pp. 1357–1362, Sept. 2009.
    [24] J. U. Knickerbocker and et al., “3-D silicon integration and silicon packaging technology using silicon
    through-vias,” IEEE Jour. of Solid-State Circuits, vol. 41, no. 8, pp. 1718–1725, Aug. 2006.
    [25] R. Chatterjee and et al., “Three dimensional chip stacking using a wafer-to-wafer integration,” in Proc. IEEE Int’l Interconnect Technology Conf., June 2007, pp. 81–83.
    [26] J. C. Koob, D. A. Leder, R. J. Sung, T. L. Brandon, D. G. Elliott, B. F. Cockburn, and L. McIlrath, “Design of a 3-D fully depleted SOI computational RAM,” IEEE Trans. on VLSI Systems, vol. 13, no. 3, pp. 358–369, March 2005.
    [27] R. S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proceedings of the IEEE, vol. 94, no. 6, pp. 1214–1224, June 2006.
    [28] Y. Xie, G. H. Loh, B. Black, and K. Bernstein, “Design space exploration for 3D architecture,” ACM Journal on Emerging Technologies in Computing Systems, vol. 2, no. 2, pp. 65–103, Apr. 2006.
    [29] P. Jacob and et al., “Mitigating memory wall effects in high-clock-rate and multicore CMOS 3-D processor memory stacks,” Proceedings of the IEEE, vol. 97, no. 1, pp. 108–122, Jan. 2009.
    [30] Y.-J. Hu, J.-F. Li, and Y.-J. Huang, “3-D content addressable memory architectures,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2009, pp. 59–64.
    [31] JEDEC, “Jedec wide I/O single data rate,” http://www.jedec.org/, Dec. 2011.
    [32] J.-S. Kim and et al., “A 1.2V 12.8 GB/s 2Gb mobile wide-I/O DRAM with 4x128 I/Os using TSV based stacking,” IEEE Jour. of Solid-State Circuits, vol. 47, no. 1, pp. 107–116, Jan. 2012.
    [33] D. Geer, “Chip makers turn to multicore processors,” IEEE Micro, vol. 38, no. 5, pp. 11–13, May 2005.
    [34] A. Agarwal and M. Levy, “The kill rule for multicore,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June 2007, pp. 750–753.
    [35] S. Borkar, “Thousand core chips - a technology perspective,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June 2007, pp. 746–749.
    [36] G. H. Loh, “3D-stacked memory architectures for multi-core processors,” in Int’l Symp. on Computer Architecture, June 2008, pp. 453–464.
    [37] H. Saito and et al., “A chip-stacked memory for on-chip SRAM-rich SoCs and processor,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), Feb. 2009, pp. 60–61.
    [38] Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, “Impacts of through-DRAM vias in 3D processor-DRAM integrated systems,” in IEEE Int’l Conf. on 3D System Integration (3DIC), Sept. 2009, pp. 1–6.
    [39] M. B. Healy and et al., “Design and analysis of 3D-MAPS: a many-core 3D processor with stacked memory,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sept. 2010, pp. 1–4.
    [40] T. Thorolfsson, K. Gonsalves, and P. D. Franzon, Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study,” in Proc. IEEE/ACM Design Automation Conf. (DAC), July 2009, pp. 51–56.
    [41] J.-F. Li and C.-W. Wu, “Is 3D integration an opportunity or just a hype?” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Jan. 2010, pp. 541–543.
    [42] H.-H. S. Lee and K. Chakrabarty, “Test challenges for 3D integrated circuits,” IEEE Design & Test of Computers, vol. 26, no. 5, pp. 26–35, Sept.-Oct. 2009.
    [43] E. J. Marinissen, “Test challenges for 3D-SICs: all the old, most of the recent, and then some new,” in Proc. Int’l Test Conf. (ITC), Nov. 2009, Panel 3.3, p. 1.
    [44] J. Verbree, E. J. Marinissen, P. Roussel, and D. Velenis, “On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking,” in Proc. IEEE European Test Symposium (ETS), Mar. 2010, pp. 36–41.
    [45] M. Taouil, S. Hamdioui, J. Verbree, and E. J. Marinissen, “On maximizing the compound yield for 3D wafter to-wafer stacked ICs,” in Proc. Int’l Test Conf. (ITC), Nov. 2010, Paper 6.2, pp. 1–10.
    [46] Y.-F. Chou, D.-M. Kwai, and C.-W.Wu, “Yield enhancement by bad-die recycling and stacking with through-silicon-via,” IEEE Trans. on VLSI Systems, vol. 19, no. 8, pp. 1346–1356, Aug. 2011.
    [47] Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W.Wu, “A built-in self-test scheme for the post-bond test of TSV in 3D ICs,” in Proc. IEEE VLSI Test Symp. (VTS),May 2011, pp. 20–25.
    [48] C.-W. Chou, Y.-J. Huang, and J.-F. Li, “Yield-enhancement techniques for 3D random access memories,” in Proc. IEEE International Symp. on VLSI Design, Automation and Test (VLSI-DAT), May 2010, pp. 104–107.
    [49] I. Parulkar and et al., “DFX of a 3rd generation, 16-core/32-thread UltraSPARC CMT microprocessor,” in Proc. Int’l Test Conf. (ITC), Oct. 2008, Paper 2.2, pp. 1–10.
    [50] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, “Test scheduling of BISTed memory cores for SOC,” in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 356–361.
    [51] A. Benso, S. D. Carlo, G. D. Natale, P. Prinetto, and M. L. Bodoni, “Programmable built-in selftesting of embedded RAM clusters in system-on-chip architectures,” IEEE Communications Magazine, vol. 41, no. 9, pp. 90–97, Sept. 2003.
    [52] R. C. Aitken, “A modular wrapper enabling high speed BIST and repair for small wide memories,” in Proc. Int’l Test Conf. (ITC), Charlotte, Oct. 2004, pp. 997–1005.
    [53] B. Wang and Q. Xu, “Test/repair area overhead reduction for small embedded memories,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2006, pp. 37–42.
    [54] L.-M. Denq and C.-W. Wu, “A hybrid BIST scheme for multiple heterogeneous embedded memories,” in Proc. IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007, pp. 349–354.
    [55] Y. Zorian and A. Yessayan, “IEEE 1500 utilization in SOC design and test,” in Proc. Int’l Test Conf.(ITC), Nov. 2005, Paper 23.2, pp. 1–10.
    [56] D.-C. Huang and W.-B. Jone, “A parallel built-in self-diagnosis method for embedded memory arrays,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 4, pp. 449–465, Apr. 2002.
    [57] Y.-J. Huang and J.-F. Li, “A low-cost pipelined BIST scheme for homogeneous RAMs in multicore chips,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2008, pp. 357–362.
    [58] S. Bahl and V. Srivastava, “Self-programmable shared BIST for testing multiple memories,” in Proc. IEEE European Test Symposium (ETS), May 2008, pp. 91–96.
    [59] Y.-J. Huang, C.-W. Chou, and J.-F. Li, “A low-cost built-in self-test scheme for an array of memories,” in Proc. IEEE European Test Symposium (ETS), May 2010, pp. 75–80.
    [60] Y.-J. Huang, Y.-C. You, and J.-F. Li, “Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs,” in Proc. IEEE International SOC Conference (SOCC), Sept. 2010, pp. 29–32.
    [61] T.-Y. Wu, P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “Improving testing and diagnosis efficiency for regular memory arrays,” in Proc. IEEE International Symp. on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2010, pp. 100–104.
    [62] A. van de Goor, G. Gaydadjiev, and S. Hamdioui, “Memory testing with a RISC microcontroller,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Mar. 2010, pp. 214–219.
    [63] P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding,” in Proc. IEEE VLSI Test Symp. (VTS), April 2010, pp. 263–268.
    [64] E. J. Marinissen, “Testing TSV-based three-dimensional stacked ICs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Mar. 2010, pp. 1689–1694.
    [65] P.-Y. Chen, C.-W.Wu, and D.-M. Kwai, “On-chip TSV testing for 3D IC before bonding using sense amplification,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2009, pp. 450–455.
    [66] T. Song, C. Liu, D. H. Kim, and S. K. Lim, “Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs,” in Proc. 12th Int’l Symp. on Quality Electronic Design (ISQED),March 2011, pp. 122–128.
    [67] J. Kim and et al., “High-frequency scalable electrical model and analysis of a through silicon via (TSV),” IEEE Trans. on Components, Packaging, and Manufacturing Technology, vol. 1, no. 2, pp. 181–195, Feb. 2011.
    [68] V. Pasca, L. Anghel, and M. Benabdenbi, “Configurable thru-silicon-via interconnect built-in self-test and diagnosis,” in 12th IEEE Latin-American Test Workshop (LATW), March 2011, pp. 1–6.
    [69] D. L. Lewis and H.-H. S. Lee, “A scan-island based design enabling pre-bond testability in die-stacked microprocessors,” in Proc. Int’l Test Conf. (ITC), Oct. 2007, Paper 21.2, pp. 1–8.
    [70] X. Wu, P. Falkenstern, and Y. Xie, “Scan chain design for three-dimensional integrated circuits (3DICs),” in Proc. IEEE Int’l Conf. on Computer Design (ICCD), Oct. 2007, pp. 208–214.
    [71] X. Wu, Y. Chen, K. Chakrabarty, and Y. Xie, “Test-access mechanism optimization for core-based three-dimensional SOCs,” in Proc. IEEE Int’l Conf. on Computer Design (ICCD), Oct. 2008, pp. 212–218.
    [72] B. Noia, K. Chakrabarty, and Y. Xie, “Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs,” in Proc. IEEE Int’l Conf. on Computer Design (ICCD), Oct. 2009, pp. 70–77.
    [73] L. Jiang, Q. Xu, K. Chakrabarty, and T. M. Mak, “Layout-driven test architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2009, pp. 191–196.
    [74] Y.-J. Huang and J.-F. Li, “Testability exploration of 3-D RAMs and CAMs,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2009, pp. 397–402.
    [75] E. J. Marinissen, J. Verbree, and M. Konijnenburg, “A structured and scalable test access architecture for TSV-based 3D stacked ICs,” in Proc. IEEE VLSI Test Symp. (VTS), May 2010, pp. 269–274.
    [76] C.-Y. Lo, Y.-T. Hsing, L.-M. Denq, and C.-W. Wu, “SOC test architecture and method for 3-D ICs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1645–1649, Oct. 2010.
    [77] C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W.Wu, “A test integration methodology for 3D integrated circuits,” in Proc. IEEE Asian Test Symp. (ATS), Dec. 2010, pp. 377–382.
    [78] M. Tsai, A. Klooz, A. Leonard, J. Appel, and P. Franzon, “Through silicon via (TSV) defect/pinhole self test circuit for 3D-IC,” in Proc. IEEE Int. Conf. 3D System Integration, Sept. 2009, pp. 1–8.
    [79] A. Rahman, S. M. Trimberger, and B. J. New, “Integrated circuit with through-die via interface for die stacking,” US Patent No. 7518398 B1, Apr. 2009.
    [80] J. Kim, F. Wang, and M. Nowak, “Method and apparatus for providing through silicon via (TSV) redundancy,” US Patent No. 20100295600 A1, Nov. 2010.
    [81] A. Ohba and et al., “A 7-ns 1-Mb BiCMOS ECL SRAM with shift redundancy,” IEEE Jour. of Solid-State Circuits, vol. 26, no. 4, pp. 507–512, April 1991.
    [82] D. Niggemeyer, M. Redeker, and J. Otterstedt, "Integration of non-classical faults in standard march tests,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 1998, pp. 91–96.
    [83] E. J. Marinissen and Y. Zorian, “IEEE std 1500 enables modular SoC testing,” IEEE Design & Test of Computers, vol. 26, no. 1, pp. 8–17, Jan.-Feb. 2009.
    [84] J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, “Detection of inter-port faults in multi-port static RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), Apr.-May 2000, pp. 297–302.
    [85] V. Iyengar, K. Chakrabarty, and E. J. Marinissen, “Test wrapper and test access mechanism cooptimization for system-on-chip,” Jour. of Electronic Testing: Theory and Applications, vol. 18, pp. 213–230, Apr. 2002.
    [86] ——, “Efficient wrapper/TAM co-optimization for large SOCs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Paris, Mar. 2002, pp. 491–498.
    [87] ——, “Integrated wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs,” in Proc. IEEE/ACM Design Automation Conf. (DAC), New Orleans, June 2002, pp. 685–690.
    [88] ——, “Test access mechanism optimization, test scheduling and tester data volume reduction for system-on-chip,” IEEE Trans. on Computers, vol. 52, no. 12, pp. 1619–1632, Dec. 2003.
    [89] Y. Huang, S. M. Reddy, W.-T. Cheng, and P. Reuter, “Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm,” in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2002, pp. 74–82.
    [90] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, “Built in self repair for embedded high density SRAM,” in Proc. Int’l Test Conf. (ITC), Oct. 1998, pp. 1112–1119.
    [91] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC yield,” IEEE Design & Test of Computers, vol. 20, pp. 58–66, May-June 2003.
    [92] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. Int’l Test Conf. (ITC), Baltimore, Oct. 2001, pp. 995–1001.
    [93] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm,” in Proc. Int’l Test Conf. (ITC), 1999, pp. 301–310.
    [94] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264,” in Proc. Int’l Test Conf. (ITC), Atlantic City, Sept. 1999, pp. 311–318.
    [95] M. Nicolaidis, N. Achouri, and S. Boutobza, “Dynamic data-bit memory built-in self-repair,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 588–594.
    [96] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories,” in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366–371.
    [97] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancies,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005.
    [98] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: an infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–1143, Oct. 2007.
    [99] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: A reconfigurable built-in self-repair scheme for random access memories in SOCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, June 2010.
    [100] T.-W. Tseng, Y.-J. Huang, and J.-F. Li, “DABISR: A defect-aware built-in self-repair scheme for single/multi-port RAMs in SOCs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1628–1639, Oct. 2010.
    [101] J.-F. Li, T.-W. Tseng, and C.-S. Hou, “Reliability-enhancement and self-repair schemes for SRAMs with static and dynamic faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 9, pp. 1361–1366, Sept 2010.
    [102] ——, “A built-in method to repair SoC RAMs in parallel,” IEEE Design & Test of Computers, vol. 27, no. 6, pp. 46–57, Nov.-Dec. 2010.
    [103] W.-B. Jone, D.-C. Huang, S.-C. Wu, and K.-J. Lee, “An efficient BIST method for small buffers,” in Proc. IEEE VLSI Test Symp. (VTS), 1999, pp. 246–251.
    [104] Y.-J. Huang and J.-F. Li, “Low-cost self-test techniques for small memories in SOCs using enhanced IEEE 1500 test wrappers,” IEEE Trans. on VLSI Systems, 2011(online).
    [105] J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang, and H.-P. Lin, “A hierarchical test scheme for system-on-chip designs,” in Proc. Conf. Design, Automation, and Test in Europe (DATE), Paris, Mar. 2002, pp. 486–490.
    [106] A. W. Topol and et al., “Enabling SOI-based assembly technology for three-dimensional(3D) integrated circuits(ICs),” in Proc. IEEE Int’ Electron Devices Meeting (IEDM), Dec. 2005, pp. 352–355.
    [107] N.Miyakawa, “A 3D prototyping chip based on a wafer-level stacking technology,” in Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC), Jan. 2009, pp. 416–420.
    [108] C.-H. Cheng, C.-K. Liu, H.-C. Liu, and K.-M. Ji, “On-line error detection and correction techniques for TSV in three-dimensional integrated circuit,” in Proc. Int’l Symp. on Intelligent Signal Processing and Communications Systems (ISPACS), Dec. 2011, pp. 1–5.
    [109] J.-F. Li, R.-S. Tzeng, and C.-W.Wu, “Diagnostic data compression techniques for embedded memories with built-in self-test,” Jour. of Electronic Testing: Theory and Applications, vol. 18, no. 4-5, pp. 515–527, Aug.-Oct. 2002.
    [110] J.-S. Choi and et al., “Antifuse EPROM circuit for field programmable DRAM,” in Proc. IEEE Int’l Solid-State Cir. Conf. (ISSCC), Feb. 2000, pp. 406–407.
    [111] M. R. Ouellette, D. L. Anand, and P. Jakobsen, “Shared fuse macro for multiple embedded memory device with redundancies,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 191–194.
    [112] D. Anand, B. Cowan, O. Fransworth, P. Jakobsen, S. Oakland, M. R. Ouellette, and D. L. Wheater, “An on-chip self-repair calculation and fusing methodology,” IEEE Design & Test of Computers, vol. 20, no. 5, pp. 67–75, Sept.-Oct. 2003.
    [113] M. Yamaoka, K. Yanagisawa, S. Shukuri, K. Norisue, and K. Ishibashi, “A system LSI memory redundancy technique using an ie-flash (inversegate-electrode flash) programming circuit,” IEEE Jour. of Solid-State Circuits, vol. 37, no. 5, pp. 599–604, May 2002.
    [114] K. Athikulwongse, A. Chakraborty, J.-S. Yang, D. Z. Pan, and S. K. Lim, “Stress-driven 3D-IC placement with TSV keep-out zone and regularity study,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2010, pp. 669–674.
    [115] M. B. Healy and S. K. Lim, “Distributed TSV topology for 3-D power-supply networks,” IEEE Trans. on VLSI Systems, 2011 (accepted).
    [116] Semiconductor Industry Association, “International technology roadmap for semiconductors (ITRS), 2009 edition,” Hsinchu, Taiwan, Dec. 2009.
    [117] C. Tian and et al., “Reliability qualification of CoSi2 electrical fuse for 90nm technology,” in Porc. IEEE Int’l Reliability Physics Symposium, Mar. 2006, pp. 392–397.
    [118] A. Sehgal, E. J. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Redundancy modelling and array yield analysis for repairable embedded memories,” IEE Proc. Computer and Digital Techniques, vol. 152, no. 1, pp. 97–106, Jan. 2005.
    [119] J. Safran and et al., “A compact eFUSE programmable array memory for SOI CMOS,” in Proc. IEEE Symp. on VLSI Circuits, June 2007, pp. 72–73.
    [120] M. Cuviello, S. Dey, X. Bai, and Y. Zhao, “Fault modeling and simulation for crosstalk in system-on-chip interconnects,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 1999, pp. 297–303.
    [121] C. Xu, H. Li, R. Suaya, and K. Banerjee, “Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs,” IEEE Trans. on Electron Devices, vol. 57, no. 12, pp. 3405–3417, Dec. 2010.
    [122] K. Sekar and S. Dey, “LI-BIST: a low-cost self-test scheme for SoC logic cores and interconnects,” in Proc. IEEE VLSI Test Symp. (VTS), May 2002, pp. 417–422.
    [123] T. Rudnicki, T. Garbolino, K. Gucwa, and A. Hlawiczka, “Effective BIST for crosstalk faults in interconnects,” in Int’l Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), April 2009, pp. 164–169.
    [124] A. Jain, B. Mandava, J. Rajski, and N. C. Rumin, “A fault-tolerant array processor designed for testability and self-reconfiguration,” IEEE Jour. of Solid-State Circuits, vol. 26, no. 5, pp. 778–788, May 1991.
    [125] L. Zhang, Y. Han, Q. Xu, X.W. Li, and H. Li, “On topology reconfiguration for defect-tolerant NoCbased homogeneous manycore systems,” IEEE Trans. on VLSI Systems, vol. 17, no. 9, pp. 1173–1186, Sept. 2009.
    [126] S. Makar, T. Altinis, N. Parkar, and J. Wu, “Testing of vega2, a chip multi-processor with spare processors,” in Proc. Int’l Test Conf. (ITC), Santa Clara, Oct. 2007, paper 9.1, pp. 1–10.
    [127] S. Shamshiri, P. Lisherness, S.-J. Pan, and K.-T. Cheng, “A cost analysis framework for multi-core systems with spares,” in Proc. Int’l Test Conf. (ITC), Oct. 2008, Paper 5.3, pp. 1–8.
    [128] L. Huang and Q. Xu, “Test economics for homogeneous manycore systems,” in Proc. Int’l Test Conf. (ITC), Oct. 2009, Paper 12.3, pp. 1–8.
    179
    [129] L. Jiang, R. Ye, and Q. Xu, “Yield enhancement for 3D-stacked memory by redundancy sharing across dies,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2010, pp. 230–234.
    [130] C. Ferri, S. Reda, and R. I. Bahar, “Parametric yield management for 3D ICs: Models and strategies for improvement,” ACM Journal on Emerging Technologies in Computing Systems(JETC), vol. 4, no. 4, pp. 19:1–19:22, Oct. 2008.
    [131] D. K. de Vries, “Investigation of gross die per wafer formulas,” IEEE Trans. on Semiconductor Manufacturing, vol. 18, no. 1, pp. 136–139, Feb. 2005.
    [132] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003.
    指導教授
  • 李進福 (Jin-Fu Li)
  • 口試日期 2012-04-18 繳交日期 2012-04-20

    [回到前頁查詢結果 | 重新搜尋]


    若有論文相關問題,請聯絡國立中央大學圖書館推廣服務組 TEL:(03)422-7151轉57407,或E-mail聯絡