碩博士論文 92521013 詳細資訊


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姓名 曾子維(Tsu-Wei Tseng)
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畢業系所 電機工程研究所(Electrical Engineering)
畢業學位 博士(Ph.D.) 畢業時期 099學年第1學期
論文名稱(中) 記憶體內建自我修復技術與設計自動化
論文名稱(英) Memory Built-In Self-Repair Techniques and Design Automation
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摘要(中) 嵌入式記憶體式系統晶片(system-on-chip, SOC)設計中之重要元件。含有數百個記憶體之系統晶片已不再陌生。此外,這些記憶體通常佔據整體系統晶片之大量面積,造成記憶體良率支配整體系統晶片之良率。因此,有效提升系統晶片中記憶體良率之技術是需要的。而記憶體內建自我修復技術(memory built-in self-repair, BISR)已被廣泛使用於提升記憶體良率。
論文的第一部分,針對多埠記憶體(multi-port RAMs)提出一瑕疵-覺知式記憶體自我修復(defect-aware BISR, DABISR)方法,可藉由定位出埠間瑕疵(inter-port defects)位置來提升多埠記憶體之修復效率。並且,我們提出了針對記憶體中字組線(word-line)間與位元線(bit-line)間埠間瑕疵定位之瑕疵定位演算法(defect-location algorithm, DLA)。DLA所存取的位址空間非常小。實驗結果顯示,所提出的瑕疵定位演算法,在20%埠間瑕疵機率假設下,對一雙埠記憶體可提升8.4%-14.4%之修復率。
論文第二部分,提出兩種分享式BISR方法,用以降低BISR於系統晶片中的面積成本。所提出的循序-分享式BISR可循序的修復多記憶體模組。其中,廣域端之備份元件分析器(redundancy analyzer)可負責待測記憶體之備份元件分析。與特定式BISR(i.e., 每一記憶體配置一獨立的BISR系統)電路比較,在四個不同尺寸記憶體的假設下,所提出之循序-分享式BISR可達成約40%-50%的節省面積比例。而為了減少面積成本且不造成長測試時間,我們也提出一平行-分享式BISR方法,可平行修復多記憶體模組。其中,廣域端之備份元件分析器可以分時多工(time multiplexing)之方式執行多記憶體模組之備份元件分析。實驗結果顯示,所提出之平行-分享式BISR之測試時間,極度接近特定式(dedicated)BISR之測試時間。然而,在五記憶體的假設下與特定式BISR比較,所提出之平行-分享式BISR可有約20%之節省面積比例。
論文第三部分,提出一記憶體BISR之設計自動化基礎框架(BISR design automation framework),可針對系統晶片中之多記憶體模組,規劃與自動產生BISR電路。所提出之BISR設計自動化基礎框架可在最大繞線之限制下,決定不同記憶體模組使用循序-分享式BISR或平行-分享式BISR電路,並且最小化整體BISR電路之面積與測試時間成本。此外,BISR相關設計參數可被最佳化使得BISR之面積成本可進一步降低。實驗結果顯示,針對50個記憶體模組,在不同功率消耗限制與最大繞線距離限制下與特定式BISR比較,所提出之BISR設計自動化基礎框架可達到約20.96%-33.67%之節省面積比例。
摘要(英) Embedded random access memory (RAM) is one key component in modern system-on-chip (SOC) designs. Several hundreds of RAM cores in a complex SOC is common. Furthermore, these RAM cores usually represent more than one half of the area of the SOC. Therefore, the yield of RAM cores dominates the yield of modern SOCs. Effective yield-enhancement techniques thus are needed for RAM cores in an SOC. Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded RAMs.
In the first part of this thesis, a defect-aware BISR (DABISR) scheme is proposed to improve the repair efficiency of multi-port RAMs (MPRAMs) by enhancing the location capability of inter-port faults caused by inter-port defects. Also, two defect-location algorithms (DLAs) are proposed to locate the inter-port defects between word-lines and bit-lines with a small range of the address space. Thus, the time complexity for executing the proposed DLAs is low. Experimental results show that the proposed defect-location algorithms can help to gain 8.4%−14.4% increase of repair rate for different redundancy configurations for a faulty two-port RAM with 20% inter-port faults.
In the second part of this thesis, two shared BISR schemes are proposed to reduce the area cost of BISR circuits in an SOC. A shared-serial BISR scheme is proposed to repair multiple RAMs sequentially. A global redundancy analyzer is responsible for performing the redundancy analysis for the RAMs under repair. In comparison with the dedicated BISR scheme, i.e., each RAM is equipped with a self-contained BISR circuit, the proposed shared-serial BISR scheme can achieve about 40%−50% ratio of the area reduction for four RAMs. To reduce the area cost without incurring long test time, a shared-parallel BISR scheme also is proposed to test and repair multiple RAMs in parallel. The shared-parallel BISR scheme consists of a global BIRA which serves multiple RAMs in time-multiplexing method. Experimental results show that the test and repair time of the shared-parallel BISR scheme approximates to that of the dedicated BISR scheme. Also, the shared-parallel BISR scheme can achieve about 20% area reduction compared with the dedicated BISR circuits for five RAMs.
In the third part of this thesis, a memory BISR design automation framework is proposed to plan and generate BISR circuits for RAMs in an SOC. The design automation framework can select the RAMs which can share a shared-serial or a shared-parallel BISR circuit under the routing distance and test power constraint, such that the number of required BISR circuits and the test time is minimized. Furthermore, design parameters of a BISR circuit can be optimized through the design automation framework such that the area cost of the BISR circuits in an SOC can be reduced further. Experimental results show that the BISR circuits generated by the proposed automation framework can save about 20.96%−33.67% area cost compared with the dedicated BISR circuits for 50 RAMs with respect to different test power constraints and distance constraints (i.e., maximum routing distance between the RAMs and the BISR circuit).
關鍵字(中)
  • 記憶體修復
  • 記憶體測試
  • 關鍵字(英)
  • memory repair
  • memory test
  • redundancy
  • yield enhancement
  • 論文目次 1 Introduction 1
    1.1 Memory Built-In Self-Repair Techniques . . . . . . . . . . . . . . . . . . . . . . 1
    1.2 Existing Memory BISR Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
    1.3 Challenges of Memory BISR Design in SOCs . . . . . . . . . . . . . . . . . . . . 13
    1.3.1 Fault-Location Problem of Typical Tests for Multi-Port RAMs . . . . . . . 14
    1.3.2 Shared BISR Techniques for RAMs . . . . . . . . . . . . . . . . . . . . . 15
    1.3.3 BISR Planning for RAMs in SOCs . . . . . . . . . . . . . . . . . . . . . . 17
    1.4 Thesis Motivations and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 20
    1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
    2 A Defect-Aware BISR Scheme for Multi-Port RAMs 26
    2.1 Fault-Location Ability of Typical Memory Test Algorithms . . . . . . . . . . . . . 27
    2.2 Proposed Defect-Aware BISR Scheme . . . . . . . . . . . . . . . . . . . . . . . . 30
    2.2.1 Block Diagram of BISR . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
    2.2.2 Redundancy Analysis Algorithm . . . . . . . . . . . . . . . . . . . . . . . 31
    2.3 Defect-Location Algorithms for Locating Bridge Defects betweenWord-lines/Bitlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
    2.3.1 Location of Bridge Defects between Word-Lines . . . . . . . . . . . . . . 32
    2.3.2 Location of Bridge Defects between Bit-Lines . . . . . . . . . . . . . . . 34
    2.3.3 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
    2.4 Design of DABISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
    2.4.1 Design of Wrapper for MPRAMs . . . . . . . . . . . . . . . . . . . . . . 37
    2.4.2 Design of BIRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
    2.5 Analysis and Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
    2.5.1 Analysis of Repair Efficiency . . . . . . . . . . . . . . . . . . . . . . . . 40
    2.5.2 Analysis of Test Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
    2.5.3 Analysis of Area Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
    2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
    3 Shared BISR Schemes for RAMs in SOCs 47
    3.1 Shared-Serial BISR Scheme for Low Area Cost . . . . . . . . . . . . . . . . . . . 48
    3.1.1 Architecture of the Shared-Serial BISR Scheme . . . . . . . . . . . . . . . 48
    3.1.2 Design of the ReBIRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
    3.1.3 Extended Shared-Serial BISR for Supporting Single-Port and Multi-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
    3.1.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
    3.2 Shared-Parallel BISR Scheme for Low Test Time . . . . . . . . . . . . . . . . . . 56
    3.2.1 Overview of the Proposed Shared Parallel BISR . . . . . . . . . . . . . . . 57
    3.2.2 Design of the Shared Parallel BISR Scheme . . . . . . . . . . . . . . . . . 59
    3.2.3 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . 66
    3.3 Chip-Level Controlling Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
    3.4 Adaptively Reconfigurable Fusing Methodology for Memory BISR . . . . . . . . 79
    3.4.1 Typical Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 79
    3.4.2 Adaptively Reconfigurable Fusing Methodology . . . . . . . . . . . . . . 81
    3.4.3 Analysis of Repair Signature Loading Time . . . . . . . . . . . . . . . . . 82
    3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
    4 Memory BISR Design Automation Framework 87
    4.1 Proposed BISR Automation Framework . . . . . . . . . . . . . . . . . . . . . . . 88
    4.2 Memory Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
    4.3 Simulation of Redundancy Configurations . . . . . . . . . . . . . . . . . . . . . . 94
    4.3.1 Simulation of Redundancy Configurations of RAMs for the Yield Maximizing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
    4.3.2 Simulation of Redundancy Configurations of RAMs for Minimizing Yield
    Degradation under AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
    4.4 BISR Scheme Allocation and Bitmap Sizing . . . . . . . . . . . . . . . . . . . . . 108
    4.4.1 BISR Scheme Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
    4.4.2 Bitmap Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
    4.5 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 114
    5 Conclusions and FutureWork 125
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    指導教授
  • 李進福 (Jin-Fu Li)
  • 口試日期 2010-11-12 繳交日期 2010-11-17

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